Commit 624009a7 authored by Mike Turquette's avatar Mike Turquette
Browse files

Merge branch 'clk-tegra-more-fixes-3.14' of... 

Merge branch 'clk-tegra-more-fixes-3.14' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes

Fixes stray access to undefined registers, use of wrong clock parents &
running clocks at wrong rates. All of these issues cause regressions in
the form of boards that are unable to boot or crash and die horrible
deaths.
parents 73640014 c7fbd415

drivers/clk/tegra/clk-divider.c

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, 
		return 0;



	if (divider_ux1 > get_max_div(divider))

		return -EINVAL;

		return get_max_div(divider);



	return divider_ux1;

}

drivers/clk/tegra/clk-id.h

+4 −0
Original line number Diff line number Diff line
@@ -180,9 +180,13 @@ enum clk_id { 
	tegra_clk_sbc6_8,

	tegra_clk_sclk,

	tegra_clk_sdmmc1,

	tegra_clk_sdmmc1_8,

	tegra_clk_sdmmc2,

	tegra_clk_sdmmc2_8,

	tegra_clk_sdmmc3,

	tegra_clk_sdmmc3_8,

	tegra_clk_sdmmc4,

	tegra_clk_sdmmc4_8,

	tegra_clk_se,

	tegra_clk_soc_therm,

	tegra_clk_sor0,

drivers/clk/tegra/clk-tegra-periph.c

+6 −4
Original line number Diff line number Diff line
@@ -371,9 +371,7 @@ static const char *mux_pllp3_pllc_clkm[] = { 
static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {

	"pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"

};

static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = {

	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,

};

#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL



static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {

	"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
@@ -465,6 +463,10 @@ static struct tegra_periph_init_data periph_clks[] = { 
	MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),

	MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),

	MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),

	MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8),

	MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8),

	MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8),

	MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4_8),

	MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),

	MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),

	MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
@@ -492,7 +494,7 @@ static struct tegra_periph_init_data periph_clks[] = { 
	UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),

	UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),

	UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),

	UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte),

	UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),

	XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),

	XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),

	XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),

drivers/clk/tegra/clk-tegra-super-gen4.c

+1 −1
Original line number Diff line number Diff line
@@ -120,7 +120,7 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base, 
					ARRAY_SIZE(cclk_lp_parents),

					CLK_SET_RATE_PARENT,

					clk_base + CCLKLP_BURST_POLICY,

					0, 4, 8, 9, NULL);

					TEGRA_DIVIDER_2, 4, 8, 9, NULL);

		*dt_clk = clk;

	}

drivers/clk/tegra/clk-tegra114.c

+4 −4
Original line number Diff line number Diff line
@@ -682,12 +682,12 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },

	[tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },

	[tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },

	[tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },

	[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },

	[tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },

	[tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },

	[tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },

	[tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },

	[tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },

	[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },

	[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },

	[tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },

	[tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },

	[tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
@@ -723,7 +723,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },

	[tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },

	[tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },

	[tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },

	[tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },

	[tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },

	[tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },

	[tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },

CRA Git | Maintained and supported by SUSTech CRA and CCSE