Commit 623a7e96 authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Remove 300Mhz minimum disp clk limit.



300Mhz disp clk limit was a workaround that was fixed in SMU and is no
longer needed.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5e3e341c
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+5 −0
Original line number Diff line number Diff line
@@ -803,6 +803,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
	if (!dcb->funcs->is_accelerated_mode(dcb))
		dc->hwss.enable_accelerated_mode(dc, context);

	dc->hwss.set_bandwidth(dc, context, false);

	/* re-program planes for existing stream, in case we need to
	 * free up plane resource for later use
	 */
@@ -869,6 +871,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
				context->streams[i]->timing.pix_clk_khz);
	}

	/* pplib is notified if disp_num changed */
	dc->hwss.set_bandwidth(dc, context, true);

	dc_enable_stereo(dc, context, dc_streams, context->stream_count);

	dc_release_state(dc->current_state);
+0 −3
Original line number Diff line number Diff line
@@ -2106,9 +2106,6 @@ enum dc_status dce110_apply_ctx_to_hw(
			return status;
	}

	/* pplib is notified if disp_num changed */
	dc->hwss.set_bandwidth(dc, context, true);

	/* to save power */
	apply_min_clocks(dc, context, &clocks_state, false);

+0 −2
Original line number Diff line number Diff line
@@ -440,8 +440,6 @@ static const struct dc_debug debug_defaults_drv = {
		.timing_trace = false,
		.clock_trace = true,

		.min_disp_clk_khz = 300000,

		.disable_pplib_clock_request = true,
		.disable_pplib_wm_range = false,
		.pplib_wm_report_mode = WM_REPORT_DEFAULT,