drm/i915/icl: Add WaEnable32PlaneMode (622b3f68) · Commits · 戴 / test

Gen11 Display suports 32 planes in total. Enable the new format in context status to be used and expanded to 32 planes. V2: Move the WA to display WA's(Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Reviewed-by:

Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:

Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:

Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181030084504.21537-1-radhakrishna.sripada@intel.com

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -2541,6 +2541,7 @@ enum i915_power_well_id {
		/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
		#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
		#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
		#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)

		/* WaClearTdlStateAckDirtyBits */
		#define GEN8_STATE_ACK _MMIO(0x20F0)

drivers/gpu/drm/i915/intel_pm.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -8854,6 +8854,10 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
		/* This is not an Wa. Enable to reduce Sampler power */
		I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
		I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);

		/* WaEnable32PlaneMode:icl */
		I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
		_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
		}

		static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)

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