Commit 621b1955 authored by Chris Metcalf's avatar Chris Metcalf
Browse files

arch/tile: support multiple huge page sizes dynamically 



This change adds support for a new "super" bit in the PTE, using the new
arch_make_huge_pte() method.  The Tilera hypervisor sees the bit set at a
given level of the page table and gangs together 4, 16, or 64 consecutive
pages from that level of the hierarchy to create a larger TLB entry.

One extra "super" page size can be specified at each of the three levels
of the page table hierarchy on tilegx, using the "hugepagesz" argument
on the boot command line.  A new hypervisor API is added to allow Linux
to tell the hypervisor how many PTEs to gang together at each level of
the page table.

To allow pre-allocating huge pages larger than the buddy allocator can
handle, this change modifies the Tilera bootmem support to put all of
memory on tilegx platforms into bootmem.

As part of this change I eliminate the vestigial CONFIG_HIGHPTE support,
which never worked anyway, and eliminate the hv_page_size() API in favor
of the standard vma_kernel_pagesize() API.

Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent d9ed9faa

arch/tile/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -47,6 +47,14 @@ config NEED_PER_CPU_PAGE_FIRST_CHUNK 
config SYS_SUPPORTS_HUGETLBFS

	def_bool y



# Support for additional huge page sizes besides HPAGE_SIZE.

# The software support is currently only present in the TILE-Gx

# hypervisor. TILEPro in any case does not support page sizes

# larger than the default HPAGE_SIZE.

config HUGETLB_SUPER_PAGES

	depends on HUGETLB_PAGE && TILEGX

	def_bool y



config GENERIC_CLOCKEVENTS

	def_bool y

arch/tile/include/asm/hugetlb.h

+21 −0
Original line number Diff line number Diff line
@@ -106,4 +106,25 @@ static inline void arch_release_hugepage(struct page *page) 
{

}



#ifdef CONFIG_HUGETLB_SUPER_PAGES

static inline pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma,

				       struct page *page, int writable)

{

	size_t pagesize = huge_page_size(hstate_vma(vma));

	if (pagesize != PUD_SIZE && pagesize != PMD_SIZE)

		entry = pte_mksuper(entry);

	return entry;

}

#define arch_make_huge_pte arch_make_huge_pte



/* Sizes to scale up page size for PTEs with HV_PTE_SUPER bit. */

enum {

	HUGE_SHIFT_PGDIR = 0,

	HUGE_SHIFT_PMD = 1,

	HUGE_SHIFT_PAGE = 2,

	HUGE_SHIFT_ENTRIES

};

extern int huge_shift[HUGE_SHIFT_ENTRIES];

#endif



#endif /* _ASM_TILE_HUGETLB_H */

arch/tile/include/asm/page.h

+2 −3
Original line number Diff line number Diff line
@@ -87,8 +87,7 @@ typedef HV_PTE pgprot_t; 
/*

 * User L2 page tables are managed as one L2 page table per page,

 * because we use the page allocator for them.  This keeps the allocation

 * simple and makes it potentially useful to implement HIGHPTE at some point.

 * However, it's also inefficient, since L2 page tables are much smaller

 * simple, but it's also inefficient, since L2 page tables are much smaller

 * than pages (currently 2KB vs 64KB).  So we should revisit this.

 */

typedef struct page *pgtable_t;
@@ -137,7 +136,7 @@ static inline __attribute_const__ int get_order(unsigned long size) 


#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)



#define HUGE_MAX_HSTATE		2

#define HUGE_MAX_HSTATE		6



#ifdef CONFIG_HUGETLB_PAGE

#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA

arch/tile/include/asm/pgtable.h

+6 −6
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ extern void set_page_homes(void); 


#define _PAGE_PRESENT           HV_PTE_PRESENT

#define _PAGE_HUGE_PAGE         HV_PTE_PAGE

#define _PAGE_SUPER_PAGE        HV_PTE_SUPER

#define _PAGE_READABLE          HV_PTE_READABLE

#define _PAGE_WRITABLE          HV_PTE_WRITABLE

#define _PAGE_EXECUTABLE        HV_PTE_EXECUTABLE
@@ -87,6 +88,7 @@ extern void set_page_homes(void); 
#define _PAGE_ALL (\

  _PAGE_PRESENT | \

  _PAGE_HUGE_PAGE | \

  _PAGE_SUPER_PAGE | \

  _PAGE_READABLE | \

  _PAGE_WRITABLE | \

  _PAGE_EXECUTABLE | \
@@ -197,6 +199,7 @@ static inline void __pte_clear(pte_t *ptep) 
#define pte_write hv_pte_get_writable

#define pte_exec hv_pte_get_executable

#define pte_huge hv_pte_get_page

#define pte_super hv_pte_get_super

#define pte_rdprotect hv_pte_clear_readable

#define pte_exprotect hv_pte_clear_executable

#define pte_mkclean hv_pte_clear_dirty
@@ -209,6 +212,7 @@ static inline void __pte_clear(pte_t *ptep) 
#define pte_mkyoung hv_pte_set_accessed

#define pte_mkwrite hv_pte_set_writable

#define pte_mkhuge hv_pte_set_page

#define pte_mksuper hv_pte_set_super



#define pte_special(pte) 0

#define pte_mkspecial(pte) (pte)
@@ -338,13 +342,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 
 */

#define pgd_offset_k(address) pgd_offset(&init_mm, address)



#if defined(CONFIG_HIGHPTE)

extern pte_t *pte_offset_map(pmd_t *, unsigned long address);

#define pte_unmap(pte) kunmap_atomic(pte)

#else

#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)

#define pte_unmap(pte) do { } while (0)

#endif



/* Clear a non-executable kernel PTE and flush it from the TLB. */

#define kpte_clear_flush(ptep, vaddr)		\
@@ -537,7 +536,8 @@ static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 
/* Support /proc/NN/pgtable API. */

struct seq_file;

int arch_proc_pgtable_show(struct seq_file *m, struct mm_struct *mm,

			   unsigned long vaddr, pte_t *ptep, void **datap);

			   unsigned long vaddr, unsigned long pagesize,

			   pte_t *ptep, void **datap);



#endif /* !__ASSEMBLY__ */

arch/tile/include/asm/tlbflush.h

+6 −11
Original line number Diff line number Diff line
@@ -38,16 +38,11 @@ DECLARE_PER_CPU(int, current_asid); 
/* The hypervisor tells us what ASIDs are available to us. */

extern int min_asid, max_asid;



static inline unsigned long hv_page_size(const struct vm_area_struct *vma)

{

	return (vma->vm_flags & VM_HUGETLB) ? HPAGE_SIZE : PAGE_SIZE;

}



/* Pass as vma pointer for non-executable mapping, if no vma available. */

#define FLUSH_NONEXEC ((const struct vm_area_struct *)-1UL)

#define FLUSH_NONEXEC ((struct vm_area_struct *)-1UL)



/* Flush a single user page on this cpu. */

static inline void local_flush_tlb_page(const struct vm_area_struct *vma,

static inline void local_flush_tlb_page(struct vm_area_struct *vma,

					unsigned long addr,

					unsigned long page_size)

{
@@ -60,7 +55,7 @@ static inline void local_flush_tlb_page(const struct vm_area_struct *vma, 
}



/* Flush range of user pages on this cpu. */

static inline void local_flush_tlb_pages(const struct vm_area_struct *vma,

static inline void local_flush_tlb_pages(struct vm_area_struct *vma,

					 unsigned long addr,

					 unsigned long page_size,

					 unsigned long len)
@@ -117,10 +112,10 @@ extern void flush_tlb_all(void); 
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);

extern void flush_tlb_current_task(void);

extern void flush_tlb_mm(struct mm_struct *);

extern void flush_tlb_page(const struct vm_area_struct *, unsigned long);

extern void flush_tlb_page_mm(const struct vm_area_struct *,

extern void flush_tlb_page(struct vm_area_struct *, unsigned long);

extern void flush_tlb_page_mm(struct vm_area_struct *,

			      struct mm_struct *, unsigned long);

extern void flush_tlb_range(const struct vm_area_struct *,

extern void flush_tlb_range(struct vm_area_struct *,

			    unsigned long start, unsigned long end);



#define flush_tlb()     flush_tlb_current_task()

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