Commit 62153bdd authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Fix readout of PIPEGCMAX 



PIPEGCMAX is a 11.6 (or 1.16 if you will) value. Ie. it can
represent a value of 1.0 when the maximum we can store in the
software LUT is 0.ffff. Clamp the value so that it gets
saturated to the max the uapi supports.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200303173313.28117-9-ville.syrjala@linux.intel.com


Reviewed-by: default avatarSwati Sharma <swati2.sharma@intel.com>
parent 0ff3b23f

drivers/gpu/drm/i915/display/intel_color.c

+2 −1
Original line number Diff line number Diff line
@@ -442,7 +442,8 @@ static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 


static u16 i965_lut_11p6_max_pack(u32 val)

{

	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);

	/* PIPEGCMAX is 11.6, clamp to 10.6 */

	return clamp_val(val, 0, 0xffff);

}



static u32 ilk_lut_10(const struct drm_color_lut *color)

drivers/gpu/drm/i915/i915_reg.h

+0 −1
Original line number Diff line number Diff line
@@ -5870,7 +5870,6 @@ enum { 


#define  _PIPEAGCMAX           0x70010

#define  _PIPEBGCMAX           0x71010

#define PIPEGCMAX_RGB_MASK     REG_GENMASK(15, 0)

#define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)



#define _PIPE_MISC_A			0x70030

CRA Git | Maintained and supported by SUSTech CRA and CCSE