Commit 61f135b9 authored by Linus Walleij's avatar Linus Walleij Committed by Dan Williams
Browse files

Add COH 901 318 DMA block driver v5 



This patch adds support for the ST-Ericsson COH 901 318 DMA block,
found in the U300 series platforms. It registers a DMA slave for
device I/O and also a memcpy slave for memcpy.

Signed-off-by: default avatarLinus Walleij <linus.walleij@stericsson.com>
Acked-by: default avatarMaciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent b419148e

arch/arm/mach-u300/include/mach/coh901318.h

0 → 100644
+281 −0
Original line number Diff line number Diff line 
/*

 *

 * include/linux/coh901318.h

 *

 *

 * Copyright (C) 2007-2009 ST-Ericsson

 * License terms: GNU General Public License (GPL) version 2

 * DMA driver for COH 901 318

 * Author: Per Friden <per.friden@stericsson.com>

 */



#ifndef COH901318_H

#define COH901318_H



#include <linux/device.h>

#include <linux/dmaengine.h>



#define MAX_DMA_PACKET_SIZE_SHIFT 11

#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)



/**

 * struct coh901318_lli - linked list item for DMAC

 * @control: control settings for DMAC

 * @src_addr: transfer source address

 * @dst_addr: transfer destination address

 * @link_addr:  physical address to next lli

 * @virt_link_addr: virtual addres of next lli (only used by pool_free)

 * @phy_this: physical address of current lli (only used by pool_free)

 */

struct coh901318_lli {

	u32 control;

	dma_addr_t src_addr;

	dma_addr_t dst_addr;

	dma_addr_t link_addr;



	void *virt_link_addr;

	dma_addr_t phy_this;

};

/**

 * struct coh901318_params - parameters for DMAC configuration

 * @config: DMA config register

 * @ctrl_lli_last: DMA control register for the last lli in the list

 * @ctrl_lli: DMA control register for an lli

 * @ctrl_lli_chained: DMA control register for a chained lli

 */

struct coh901318_params {

	u32 config;

	u32 ctrl_lli_last;

	u32 ctrl_lli;

	u32 ctrl_lli_chained;

};

/**

 * struct coh_dma_channel - dma channel base

 * @name: ascii name of dma channel

 * @number: channel id number

 * @desc_nbr_max: number of preallocated descriptortors

 * @priority_high: prio of channel, 0 low otherwise high.

 * @param: configuration parameters

 * @dev_addr: physical address of periphal connected to channel

 */

struct coh_dma_channel {

	const char name[32];

	const int number;

	const int desc_nbr_max;

	const int priority_high;

	const struct coh901318_params param;

	const dma_addr_t dev_addr;

};



/**

 * dma_access_memory_state_t - register dma for memory access

 *

 * @dev: The dma device

 * @active:  1 means dma intends to access memory

 *           0 means dma wont access memory

 */

typedef void (*dma_access_memory_state_t)(struct device *dev,

					  bool active);



/**

 * struct powersave - DMA power save structure

 * @lock: lock protecting data in this struct

 * @started_channels: bit mask indicating active dma channels

 */

struct powersave {

	spinlock_t lock;

	u64 started_channels;

};

/**

 * struct coh901318_platform - platform arch structure

 * @chans_slave: specifying dma slave channels

 * @chans_memcpy: specifying dma memcpy channels

 * @access_memory_state: requesting DMA memeory access (on / off)

 * @chan_conf: dma channel configurations

 * @max_channels: max number of dma chanenls

 */

struct coh901318_platform {

	const int *chans_slave;

	const int *chans_memcpy;

	const dma_access_memory_state_t access_memory_state;

	const struct coh_dma_channel *chan_conf;

	const int max_channels;

};



/**

 * coh901318_get_bytes_left() - Get number of bytes left on a current transfer

 * @chan: dma channel handle

 * return number of bytes left, or negative on error

 */

u32 coh901318_get_bytes_left(struct dma_chan *chan);



/**

 * coh901318_stop() - Stops dma transfer

 * @chan: dma channel handle

 * return 0 on success otherwise negative value

 */

void coh901318_stop(struct dma_chan *chan);



/**

 * coh901318_continue() - Resumes a stopped dma transfer

 * @chan: dma channel handle

 * return 0 on success otherwise negative value

 */

void coh901318_continue(struct dma_chan *chan);



/**

 * coh901318_filter_id() - DMA channel filter function

 * @chan: dma channel handle

 * @chan_id: id of dma channel to be filter out

 *

 * In dma_request_channel() it specifies what channel id to be requested

 */

bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);



/*

 * DMA Controller - this access the static mappings of the coh901318 dma.

 *

 */



#define COH901318_MOD32_MASK					(0x1F)

#define COH901318_WORD_MASK					(0xFFFFFFFF)

/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */

#define COH901318_INT_STATUS1					(0x0000)

#define COH901318_INT_STATUS2					(0x0004)

/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */

#define COH901318_TC_INT_STATUS1				(0x0008)

#define COH901318_TC_INT_STATUS2				(0x000C)

/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */

#define COH901318_TC_INT_CLEAR1					(0x0010)

#define COH901318_TC_INT_CLEAR2					(0x0014)

/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */

#define COH901318_RAW_TC_INT_STATUS1				(0x0018)

#define COH901318_RAW_TC_INT_STATUS2				(0x001C)

/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */

#define COH901318_BE_INT_STATUS1				(0x0020)

#define COH901318_BE_INT_STATUS2				(0x0024)

/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */

#define COH901318_BE_INT_CLEAR1					(0x0028)

#define COH901318_BE_INT_CLEAR2					(0x002C)

/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */

#define COH901318_RAW_BE_INT_STATUS1				(0x0030)

#define COH901318_RAW_BE_INT_STATUS2				(0x0034)



/*

 * CX_CFG - Channel Configuration Registers 32bit (R/W)

 */

#define COH901318_CX_CFG					(0x0100)

#define COH901318_CX_CFG_SPACING				(0x04)

/* Channel enable activates tha dma job */

#define COH901318_CX_CFG_CH_ENABLE				(0x00000001)

#define COH901318_CX_CFG_CH_DISABLE				(0x00000000)

/* Request Mode */

#define COH901318_CX_CFG_RM_MASK				(0x00000006)

#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY			(0x0 << 1)

#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY			(0x1 << 1)

#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY			(0x1 << 1)

#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY		(0x3 << 1)

#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY		(0x3 << 1)

/* Linked channel request field. RM must == 11 */

#define COH901318_CX_CFG_LCRF_SHIFT				3

#define COH901318_CX_CFG_LCRF_MASK				(0x000001F8)

#define COH901318_CX_CFG_LCR_DISABLE				(0x00000000)

/* Terminal Counter Interrupt Request Mask */

#define COH901318_CX_CFG_TC_IRQ_ENABLE				(0x00000200)

#define COH901318_CX_CFG_TC_IRQ_DISABLE				(0x00000000)

/* Bus Error interrupt Mask */

#define COH901318_CX_CFG_BE_IRQ_ENABLE				(0x00000400)

#define COH901318_CX_CFG_BE_IRQ_DISABLE				(0x00000000)



/*

 * CX_STAT - Channel Status Registers 32bit (R/-)

 */

#define COH901318_CX_STAT					(0x0200)

#define COH901318_CX_STAT_SPACING				(0x04)

#define COH901318_CX_STAT_RBE_IRQ_IND				(0x00000008)

#define COH901318_CX_STAT_RTC_IRQ_IND				(0x00000004)

#define COH901318_CX_STAT_ACTIVE				(0x00000002)

#define COH901318_CX_STAT_ENABLED				(0x00000001)



/*

 * CX_CTRL - Channel Control Registers 32bit (R/W)

 */

#define COH901318_CX_CTRL					(0x0400)

#define COH901318_CX_CTRL_SPACING				(0x10)

/* Transfer Count Enable */

#define COH901318_CX_CTRL_TC_ENABLE				(0x00001000)

#define COH901318_CX_CTRL_TC_DISABLE				(0x00000000)

/* Transfer Count Value 0 - 4095 */

#define COH901318_CX_CTRL_TC_VALUE_MASK				(0x00000FFF)

/* Burst count */

#define COH901318_CX_CTRL_BURST_COUNT_MASK			(0x0000E000)

#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES			(0x7 << 13)

#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES			(0x6 << 13)

#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES			(0x5 << 13)

#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES			(0x4 << 13)

#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES			(0x3 << 13)

#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES			(0x2 << 13)

#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES			(0x1 << 13)

#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE			(0x0 << 13)

/* Source bus size  */

#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK			(0x00030000)

#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS			(0x2 << 16)

#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS			(0x1 << 16)

#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS			(0x0 << 16)

/* Source address increment */

#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE			(0x00040000)

#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE			(0x00000000)

/* Destination Bus Size */

#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK			(0x00180000)

#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS			(0x2 << 19)

#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS			(0x1 << 19)

#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS			(0x0 << 19)

/* Destination address increment */

#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE			(0x00200000)

#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE			(0x00000000)

/* Master Mode (Master2 is only connected to MSL) */

#define COH901318_CX_CTRL_MASTER_MODE_MASK			(0x00C00000)

#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W			(0x3 << 22)

#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W			(0x2 << 22)

#define COH901318_CX_CTRL_MASTER_MODE_M2RW			(0x1 << 22)

#define COH901318_CX_CTRL_MASTER_MODE_M1RW			(0x0 << 22)

/* Terminal Count flag to PER enable */

#define COH901318_CX_CTRL_TCP_ENABLE				(0x01000000)

#define COH901318_CX_CTRL_TCP_DISABLE				(0x00000000)

/* Terminal Count flags to CPU enable */

#define COH901318_CX_CTRL_TC_IRQ_ENABLE				(0x02000000)

#define COH901318_CX_CTRL_TC_IRQ_DISABLE			(0x00000000)

/* Hand shake to peripheral */

#define COH901318_CX_CTRL_HSP_ENABLE				(0x04000000)

#define COH901318_CX_CTRL_HSP_DISABLE				(0x00000000)

#define COH901318_CX_CTRL_HSS_ENABLE				(0x08000000)

#define COH901318_CX_CTRL_HSS_DISABLE				(0x00000000)

/* DMA mode */

#define COH901318_CX_CTRL_DDMA_MASK				(0x30000000)

#define COH901318_CX_CTRL_DDMA_LEGACY				(0x0 << 28)

#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1			(0x1 << 28)

#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2			(0x2 << 28)

/* Primary Request Data Destination */

#define COH901318_CX_CTRL_PRDD_MASK				(0x40000000)

#define COH901318_CX_CTRL_PRDD_DEST				(0x1 << 30)

#define COH901318_CX_CTRL_PRDD_SOURCE				(0x0 << 30)



/*

 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)

 */

#define COH901318_CX_SRC_ADDR					(0x0404)

#define COH901318_CX_SRC_ADDR_SPACING				(0x10)



/*

 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W

 */

#define COH901318_CX_DST_ADDR					(0x0408)

#define COH901318_CX_DST_ADDR_SPACING				(0x10)



/*

 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)

 */

#define COH901318_CX_LNK_ADDR					(0x040C)

#define COH901318_CX_LNK_ADDR_SPACING				(0x10)

#define COH901318_CX_LNK_LINK_IMMEDIATE				(0x00000001)

#endif /* COH901318_H */

drivers/dma/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -109,6 +109,13 @@ config SH_DMAE 
	help

	  Enable support for the Renesas SuperH DMA controllers.



config COH901318

	bool "ST-Ericsson COH901318 DMA support"

	select DMA_ENGINE

	depends on ARCH_U300

	help

	  Enable support for ST-Ericsson COH 901 318 DMA.



config DMA_ENGINE

	bool

drivers/dma/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,3 +10,4 @@ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o 
obj-$(CONFIG_MX3_IPU) += ipu/

obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o

obj-$(CONFIG_SH_DMAE) += shdma.o

obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o

drivers/dma/coh901318.c

0 → 100644
+1325 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/dma/coh901318_lli.c

0 → 100644
+318 −0
Original line number Diff line number Diff line 
/*

 * driver/dma/coh901318_lli.c

 *

 * Copyright (C) 2007-2009 ST-Ericsson

 * License terms: GNU General Public License (GPL) version 2

 * Support functions for handling lli for dma

 * Author: Per Friden <per.friden@stericsson.com>

 */



#include <linux/dma-mapping.h>

#include <linux/spinlock.h>

#include <linux/dmapool.h>

#include <linux/memory.h>

#include <mach/coh901318.h>



#include "coh901318_lli.h"



#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))

#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)

#define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)

#else

#define DEBUGFS_POOL_COUNTER_RESET(pool)

#define DEBUGFS_POOL_COUNTER_ADD(pool, add)

#endif



static struct coh901318_lli *

coh901318_lli_next(struct coh901318_lli *data)

{

	if (data == NULL || data->link_addr == 0)

		return NULL;



	return (struct coh901318_lli *) data->virt_link_addr;

}



int coh901318_pool_create(struct coh901318_pool *pool,

			  struct device *dev,

			  size_t size, size_t align)

{

	spin_lock_init(&pool->lock);

	pool->dev = dev;

	pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);



	DEBUGFS_POOL_COUNTER_RESET(pool);

	return 0;

}



int coh901318_pool_destroy(struct coh901318_pool *pool)

{



	dma_pool_destroy(pool->dmapool);

	return 0;

}



struct coh901318_lli *

coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)

{

	int i;

	struct coh901318_lli *head;

	struct coh901318_lli *lli;

	struct coh901318_lli *lli_prev;

	dma_addr_t phy;



	if (len == 0)

		goto err;



	spin_lock(&pool->lock);



	head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);



	if (head == NULL)

		goto err;



	DEBUGFS_POOL_COUNTER_ADD(pool, 1);



	lli = head;

	lli->phy_this = phy;



	for (i = 1; i < len; i++) {

		lli_prev = lli;



		lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);



		if (lli == NULL)

			goto err_clean_up;



		DEBUGFS_POOL_COUNTER_ADD(pool, 1);

		lli->phy_this = phy;



		lli_prev->link_addr = phy;

		lli_prev->virt_link_addr = lli;

	}



	lli->link_addr = 0x00000000U;



	spin_unlock(&pool->lock);



	return head;



 err:

	spin_unlock(&pool->lock);

	return NULL;



 err_clean_up:

	lli_prev->link_addr = 0x00000000U;

	spin_unlock(&pool->lock);

	coh901318_lli_free(pool, &head);

	return NULL;

}



void coh901318_lli_free(struct coh901318_pool *pool,

			struct coh901318_lli **lli)

{

	struct coh901318_lli *l;

	struct coh901318_lli *next;



	if (lli == NULL)

		return;



	l = *lli;



	if (l == NULL)

		return;



	spin_lock(&pool->lock);



	while (l->link_addr) {

		next = l->virt_link_addr;

		dma_pool_free(pool->dmapool, l, l->phy_this);

		DEBUGFS_POOL_COUNTER_ADD(pool, -1);

		l = next;

	}

	dma_pool_free(pool->dmapool, l, l->phy_this);

	DEBUGFS_POOL_COUNTER_ADD(pool, -1);



	spin_unlock(&pool->lock);

	*lli = NULL;

}



int

coh901318_lli_fill_memcpy(struct coh901318_pool *pool,

			  struct coh901318_lli *lli,

			  dma_addr_t source, unsigned int size,

			  dma_addr_t destination, u32 ctrl_chained,

			  u32 ctrl_eom)

{

	int s = size;

	dma_addr_t src = source;

	dma_addr_t dst = destination;



	lli->src_addr = src;

	lli->dst_addr = dst;



	while (lli->link_addr) {

		lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;

		lli->src_addr = src;

		lli->dst_addr = dst;



		s -= MAX_DMA_PACKET_SIZE;

		lli = coh901318_lli_next(lli);



		src += MAX_DMA_PACKET_SIZE;

		dst += MAX_DMA_PACKET_SIZE;

	}



	lli->control = ctrl_eom | s;

	lli->src_addr = src;

	lli->dst_addr = dst;



	/* One irq per single transfer */

	return 1;

}



int

coh901318_lli_fill_single(struct coh901318_pool *pool,

			  struct coh901318_lli *lli,

			  dma_addr_t buf, unsigned int size,

			  dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,

			  enum dma_data_direction dir)

{

	int s = size;

	dma_addr_t src;

	dma_addr_t dst;





	if (dir == DMA_TO_DEVICE) {

		src = buf;

		dst = dev_addr;



	} else if (dir == DMA_FROM_DEVICE) {



		src = dev_addr;

		dst = buf;

	} else {

		return -EINVAL;

	}



	while (lli->link_addr) {

		size_t block_size = MAX_DMA_PACKET_SIZE;

		lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;



		/* If we are on the next-to-final block and there will

		 * be less than half a DMA packet left for the last

		 * block, then we want to make this block a little

		 * smaller to balance the sizes. This is meant to

		 * avoid too small transfers if the buffer size is

		 * (MAX_DMA_PACKET_SIZE*N + 1) */

		if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))

			block_size = MAX_DMA_PACKET_SIZE/2;



		s -= block_size;

		lli->src_addr = src;

		lli->dst_addr = dst;



		lli = coh901318_lli_next(lli);



		if (dir == DMA_TO_DEVICE)

			src += block_size;

		else if (dir == DMA_FROM_DEVICE)

			dst += block_size;

	}



	lli->control = ctrl_eom | s;

	lli->src_addr = src;

	lli->dst_addr = dst;



	/* One irq per single transfer */

	return 1;

}



int

coh901318_lli_fill_sg(struct coh901318_pool *pool,

		      struct coh901318_lli *lli,

		      struct scatterlist *sgl, unsigned int nents,

		      dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,

		      u32 ctrl_last,

		      enum dma_data_direction dir, u32 ctrl_irq_mask)

{

	int i;

	struct scatterlist *sg;

	u32 ctrl_sg;

	dma_addr_t src = 0;

	dma_addr_t dst = 0;

	int nbr_of_irq = 0;

	u32 bytes_to_transfer;

	u32 elem_size;



	if (lli == NULL)

		goto err;



	spin_lock(&pool->lock);



	if (dir == DMA_TO_DEVICE)

		dst = dev_addr;

	else if (dir == DMA_FROM_DEVICE)

		src = dev_addr;

	else

		goto err;



	for_each_sg(sgl, sg, nents, i) {

		if (sg_is_chain(sg)) {

			/* sg continues to the next sg-element don't

			 * send ctrl_finish until the last

			 * sg-element in the chain

			 */

			ctrl_sg = ctrl_chained;

		} else if (i == nents - 1)

			ctrl_sg = ctrl_last;

		else

			ctrl_sg = ctrl ? ctrl : ctrl_last;





		if ((ctrl_sg & ctrl_irq_mask))

			nbr_of_irq++;



		if (dir == DMA_TO_DEVICE)

			/* increment source address */

			src = sg_dma_address(sg);

		else

			/* increment destination address */

			dst =  sg_dma_address(sg);



		bytes_to_transfer = sg_dma_len(sg);



		while (bytes_to_transfer) {

			u32 val;



			if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {

				elem_size = MAX_DMA_PACKET_SIZE;

				val = ctrl_chained;

			} else {

				elem_size = bytes_to_transfer;

				val = ctrl_sg;

			}



			lli->control = val | elem_size;

			lli->src_addr = src;

			lli->dst_addr = dst;



			if (dir == DMA_FROM_DEVICE)

				dst += elem_size;

			else

				src += elem_size;



			BUG_ON(lli->link_addr & 3);



			bytes_to_transfer -= elem_size;

			lli = coh901318_lli_next(lli);

		}



	}

	spin_unlock(&pool->lock);



	/* There can be many IRQs per sg transfer */

	return nbr_of_irq;

 err:

	spin_unlock(&pool->lock);

	return -EINVAL;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE