Commit 61e50646 authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher
Browse files

drm/amd/display: add Pollock IDs, fix Pollock & Dali clk mgr construct 



[WHY]
Only a single voltage level should be available to Pollock (min level)
Pollock & Dali get misidentified as Renoir, use wrong clk mgr constructor

[HOW]
Add provided Pollock IDs to ASIC Rev. ID list.
Create new Pollock ASIC RID check, fix RV2 & Dali ASIC checks.
Check RID and set max voltage level to 0 if Pollock is detected.
Work around broken ASICREV_IS_RENOIR, IS_RAVEN2, etc. checks by
performing Dali/Pollock checks before they can be misidentified as RN.

Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eee2eaba

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+2 −2
Original line number Diff line number Diff line
@@ -705,8 +705,8 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v, 


unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)

{

	/* for dali, the highest voltage level we want is 0 */

	if (ASICREV_IS_DALI(hw_internal_rev))

	/* for dali & pollock, the highest voltage level we want is 0 */

	if (ASICREV_IS_POLLOCK(hw_internal_rev) || ASICREV_IS_DALI(hw_internal_rev))

		return 0;



	/* we are ok with all levels */

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+3 −3
Original line number Diff line number Diff line
@@ -134,13 +134,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p 


#if defined(CONFIG_DRM_AMD_DC_DCN)

	case FAMILY_RV:

		if (ASICREV_IS_DALI(asic_id.hw_internal_rev)) {

		if (ASICREV_IS_DALI(asic_id.hw_internal_rev) ||

				ASICREV_IS_POLLOCK(asic_id.hw_internal_rev)) {

			/* TEMP: this check has to come before ASICREV_IS_RENOIR */

			/* which also incorrectly returns true for Dali */

			/* which also incorrectly returns true for Dali/Pollock*/

			rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);

			break;

		}



		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {

			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

			break;

drivers/gpu/drm/amd/display/include/dal_asic_id.h

+10 −0
Original line number Diff line number Diff line
@@ -134,8 +134,13 @@ 
#define PICASSO_A0 0x41

/* DCN1_01 */

#define RAVEN2_A0 0x81

#define RAVEN2_15D8_REV_94 0x94

#define RAVEN2_15D8_REV_95 0x95

#define RAVEN2_15D8_REV_E3 0xE3

#define RAVEN2_15D8_REV_E4 0xE4

#define RAVEN2_15D8_REV_E9 0xE9

#define RAVEN2_15D8_REV_EA 0xEA

#define RAVEN2_15D8_REV_EB 0xEB

#define RAVEN1_F0 0xF0

#define RAVEN_UNKNOWN 0xFF

#ifndef ASICREV_IS_RAVEN
@@ -149,6 +154,11 @@ 
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))

#define ASICREV_IS_DALI(eChipRev) ((eChipRev == RAVEN2_15D8_REV_E3) \

		|| (eChipRev == RAVEN2_15D8_REV_E4))

#define ASICREV_IS_POLLOCK(eChipRev) (eChipRev == RAVEN2_15D8_REV_94 \

		|| eChipRev == RAVEN2_15D8_REV_95 \

			|| eChipRev == RAVEN2_15D8_REV_E9 \

				|| eChipRev == RAVEN2_15D8_REV_EA \

					|| eChipRev == RAVEN2_15D8_REV_EB)



#define FAMILY_RV 142 /* DCN 1*/

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