Commit 61b088c5 authored by Swathi Dhanavanthri's avatar Swathi Dhanavanthri Committed by José Roberto de Souza
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drm/i915/ehl: Restrict w/a 1607087056 for EHL/JSL



This w/a is fixed in B0 stepping and needs to be restricted for
A0 stepping only.
Bspec: 33451

Signed-off-by: default avatarSwathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200512180050.6785-1-swathi.dhanavanthri@intel.com
parent 73e28cc4
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+7 −4
Original line number Diff line number Diff line
@@ -917,11 +917,14 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
		    GAMT_CHKN_BIT_REG,
		    GAMT_CHKN_DISABLE_L3_COH_PIPE);

	/* Wa_1607087056:icl */
	/* Wa_1607087056:icl,ehl,jsl */
	if (IS_ICELAKE(i915) ||
	    IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
		wa_write_or(wal,
			    SLICE_UNIT_LEVEL_CLKGATE,
			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
	}
}

static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+5 −0
Original line number Diff line number Diff line
@@ -1514,6 +1514,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ICL_REVID(p, since, until) \
	(IS_ICELAKE(p) && IS_REVID(p, since, until))

#define EHL_REVID_A0            0x0

#define IS_EHL_REVID(p, since, until) \
	(IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))

#define TGL_REVID_A0		0x0
#define TGL_REVID_B0		0x1
#define TGL_REVID_C0		0x2