Commit 61939d97 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: implement WaForceL3Serialization on VLV and IVB 

References: https://bugs.freedesktop.org/show_bug.cgi?id=50250


Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ff1f525e

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -3448,6 +3448,9 @@ 
#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030

#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000



#define GEN7_L3SQCREG4				0xb034

#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)



/* WaCatErrorRejectionIssue */

#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030

#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)

drivers/gpu/drm/i915/intel_pm.c

+8 −0
Original line number Diff line number Diff line
@@ -3547,6 +3547,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

			GEN7_WA_L3_CHICKEN_MODE);



	/* WaForceL3Serialization */

	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &

		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);



	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock

	 * gating disable must be set.  Failure to set it results in

	 * flickering pixels due to Z write ordering failures after
@@ -3617,6 +3621,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);

	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);



	/* WaForceL3Serialization */

	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &

		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);



	/* This is required by WaCatErrorRejectionIssue */

	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

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