Commit 6160aca4 authored Oct 28, 2020 by Nicolin Chen Committed by Thierry Reding Nov 20, 2020

clk: tegra: Do not return 0 on failure



Return values from read_dt_param() will be either TRUE (1) or
FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
or an ERR code on failure.

So this patch fixes the bug of returning 0 on failure.

Fixes: 36541f04 ("clk: tegra: dfll: support PWM regulator control")
Cc: <stable@vger.kernel.org>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent 3650b228

drivers/clk/tegra/clk-dfll.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1856,13 +1856,13 @@ static int dfll_fetch_pwm_params(struct tegra_dfll *td)
		&td->reg_init_uV);
		if (!ret) {
		dev_err(td->dev, "couldn't get initialized voltage\n");
		return ret;
		return -EINVAL;
		}

		ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
		if (!ret) {
		dev_err(td->dev, "couldn't get PWM period\n");
		return ret;
		return -EINVAL;
		}
		td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);

Admin message