Commit 615b9b58 authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
Browse files

drm/amd/display: Fix update_bw_bounding_box Calcs



[Why]
Previously update_bw_bounding_box for RN was commented out
due to incorrect values causing BSOD on Hybrid Graphics.
However, commenting out this function also may cause issues
such as underflow in certain cases such as 2x4K displays.

[How]
Fix dram_speed_mts calculations.
Update from proper index of clock_limits[]

Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 302f5988
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+2 −9
Original line number Diff line number Diff line
@@ -1323,12 +1323,6 @@ struct display_stream_compressor *dcn21_dsc_create(

static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
	/*
	TODO: Fix this function to calcualte correct values.
	There are known issues with this function currently
	that will need to be investigated. Use hardcoded known good values for now.


	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
	struct clk_limit_table *clk_table = &bw_params->clk_table;
	int i;
@@ -1343,11 +1337,10 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
		dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
		dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
		dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
	}
	dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
	dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - 1];
	dcn2_1_soc.num_states = i;
	*/
}

/* Temporary Place holder until we can get them from fuse */