Commit 613880a1 authored May 07, 2015 by Robert Schwebel Committed by Arnd Bergmann May 12, 2015

ARM: vexpress/ca9: Add interrupt-affinity to the PMU node



Commit 9fd85eb5 ("ARM: pmu: add support for interrupt-affinity
property") added an optional "interrupt-affinity" property, to specify
the CPU affinity for each SPI listed in the interrupts property.

Without this property, we get this boot warning:

  CPU PMU: Failed to parse <no-node>/interrupt-affinity[0]

This patch adds interrupt-affinity to the PMU node in the
vexpress-v2p-ca9 device tree.

Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parent 2004f98a

arch/arm/boot/dts/vexpress-v2p-ca9.dts

+6 −4

Original line number	Diff line number	Diff line
		@@ -33,28 +33,28 @@
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		A9_0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a9";
		reg = <0>;
		next-level-cache = <&L2>;
		};

		cpu@1 {
		A9_1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a9";
		reg = <1>;
		next-level-cache = <&L2>;
		};

		cpu@2 {
		A9_2: cpu@2 {
		device_type = "cpu";
		compatible = "arm,cortex-a9";
		reg = <2>;
		next-level-cache = <&L2>;
		};

		cpu@3 {
		A9_3: cpu@3 {
		device_type = "cpu";
		compatible = "arm,cortex-a9";
		reg = <3>;
		@@ -182,6 +182,8 @@
		<0 61 4>,
		<0 62 4>,
		<0 63 4>;
		interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;

		};

		dcc {

Admin message