drm/msm: Use drm_mode_vrefresh instead of mode->vrefresh (6117f862) · Commits · 戴 / test

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -521,7 +521,7 @@ static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
		list_for_each_entry(cur_mode, &connector->modes, head) {
		if (cur_mode->vdisplay == adj_mode->vdisplay &&
		cur_mode->hdisplay == adj_mode->hdisplay &&
		cur_mode->vrefresh == adj_mode->vrefresh) {
		drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) {
		adj_mode->private = cur_mode->private;
		adj_mode->private_flags \|= cur_mode->private_flags;
		}
		@@ -1802,7 +1802,7 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc, bool async)

		atomic_set(&dpu_enc->frame_done_timeout,
		DPU_FRAME_DONE_TIMEOUT * 1000 /
		drm_enc->crtc->state->adjusted_mode.vrefresh);
		drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode));
		mod_timer(&dpu_enc->frame_done_timer, jiffies +
		((atomic_read(&dpu_enc->frame_done_timeout) * HZ) / 1000));

+3 −2

Original line number	Diff line number	Diff line
		@@ -404,7 +404,8 @@ static void dpu_encoder_phys_cmd_tearcheck_config(
		return;
		}

		tc_cfg.vsync_count = vsync_hz / (mode->vtotal * mode->vrefresh);
		tc_cfg.vsync_count = vsync_hz /
		(mode->vtotal * drm_mode_vrefresh(mode));

		/* enable external TE after kickoff to avoid premature autorefresh */
		tc_cfg.hw_vsync_mode = 0;
		@@ -424,7 +425,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config(
		DPU_DEBUG_CMDENC(cmd_enc,
		"tc %d vsync_clk_speed_hz %u vtotal %u vrefresh %u\n",
		phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz,
		mode->vtotal, mode->vrefresh);
		mode->vtotal, drm_mode_vrefresh(mode));
		DPU_DEBUG_CMDENC(cmd_enc,
		"tc %d enable %u start_pos %u rd_ptr_irq %u\n",
		phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos,

+1 −1

Original line number	Diff line number	Diff line
		@@ -387,7 +387,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
		ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
		ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
		ot_params.is_wfd = !pdpu->is_rt_pipe;
		ot_params.frame_rate = crtc->mode.vrefresh;
		ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
		ot_params.vbif_idx = VBIF_RT;
		ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
		ot_params.rd = true;

+2 −2

Original line number	Diff line number	Diff line
		@@ -59,10 +59,10 @@ static int pingpong_tearcheck_setup(struct drm_encoder *encoder,
		return -EINVAL;
		}

		total_lines_x100 = mode->vtotal * mode->vrefresh;
		total_lines_x100 = mode->vtotal * drm_mode_vrefresh(mode);
		if (!total_lines_x100) {
		DRM_DEV_ERROR(dev, "%s: vtotal(%d) or vrefresh(%d) is 0\n",
		__func__, mode->vtotal, mode->vrefresh);
		__func__, mode->vtotal, drm_mode_vrefresh(mode));
		return -EINVAL;
		}