drivers/clk/at91/clk-peripheral.c
0 → 100644
+410
−0
+9
−0
+5
−0
Loading
Gitlab 现已全面支持 git over ssh 与 git over https。通过 HTTPS 访问请配置带有 read_repository / write_repository 权限的 Personal access token。通过 SSH 端口访问请使用 22 端口或 13389 端口。如果使用CAS注册了账户但不知道密码,可以自行至设置中更改;如有其他问题,请发邮件至 service@cra.moe 寻求协助。
This patch adds new at91 peripheral clock implementation using common clk framework. Almost all peripherals provided by at91 SoCs need a clock to work properly. This clock is enabled/disabled using PCER/PCDR resgisters. Each peripheral is given an id (see atmel's datasheets) which is used to define and reference peripheral clocks. Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you can configure the peripheral clock as a division of the master clock. This will help reducing the peripherals power comsumption. Signed-off-by:Boris BREZILLON <b.brezillon@overkiz.com> Acked-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
CRA Git | Maintained and supported by SUSTech CRA and CCSE