Commit 60f2f749 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2020-12-07' of https://gitlab.freedesktop.org/drm/msm into drm-next 



* Shutdown hook for GPU (to ensure GPU is idle before iommu goes away)
* GPU cooling device support
* DSI 7nm and 10nm phy/pll updates
* Additional sm8150/sm8250 DPU support (merge_3d and DSPP color
  processing)
* Various DP fixes
* A whole bunch of W=1 fixes from Lee Jones
* GEM locking re-work (no more trylock_recursive in shrinker!)
* LLCC (system cache) support
* Various other fixes/cleanups

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGt0G=H3_RbF_GAQv838z5uujSmFd+7fYhL6Yg=23LwZ=g@mail.gmail.com
parents 5eb3c85e e319a1b9

Documentation/devicetree/bindings/display/msm/gpu.txt

+7 −0
Original line number Diff line number Diff line
@@ -39,6 +39,10 @@ Required properties: 
        a4xx Snapdragon SoCs. See

        Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.



Optional properties:

- #cooling-cells: The value must be 2. For details, please refer

	Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.



Example 3xx/4xx:



/ {
@@ -61,6 +65,7 @@ Example 3xx/4xx: 
		power-domains = <&mmcc OXILICX_GDSC>;

		operating-points-v2 = <&gpu_opp_table>;

		iommus = <&gpu_iommu 0>;

		#cooling-cells = <2>;

	};



	gpu_sram: ocmem@fdd00000 {
@@ -98,6 +103,8 @@ Example a6xx (with GMU): 
		reg = <0x5000000 0x40000>, <0x509e000 0x10>;

		reg-names = "kgsl_3d0_reg_memory", "cx_mem";



		#cooling-cells = <2>;



		/*

		 * Look ma, no clocks! The GPU clocks and power are

		 * controlled entirely by the GMU

drivers/gpu/drm/msm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ config DRM_MSM 
	tristate "MSM DRM"

	depends on DRM

	depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST)

	depends on IOMMU_SUPPORT

	depends on OF && COMMON_CLK

	depends on MMU

	depends on QCOM_OCMEM || QCOM_OCMEM=n

	select IOMMU_IO_PGTABLE

	select QCOM_MDT_LOADER if ARCH_QCOM

drivers/gpu/drm/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ msm-y := \ 
	disp/dpu1/dpu_hw_pingpong.o \

	disp/dpu1/dpu_hw_sspp.o \

	disp/dpu1/dpu_hw_dspp.o \

	disp/dpu1/dpu_hw_merge3d.o \

	disp/dpu1/dpu_hw_top.o \

	disp/dpu1/dpu_hw_util.o \

	disp/dpu1/dpu_hw_vbif.o \

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+19 −2
Original line number Diff line number Diff line
@@ -519,6 +519,8 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) 
	struct msm_gpu *gpu;

	struct msm_drm_private *priv = dev->dev_private;

	struct platform_device *pdev = priv->gpu_pdev;

	struct icc_path *ocmem_icc_path;

	struct icc_path *icc_path;

	int ret;



	if (!pdev) {
@@ -566,13 +568,28 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) 
		goto fail;

	}



	icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");

	ret = IS_ERR(icc_path);

	if (ret)

		goto fail;



	ocmem_icc_path = devm_of_icc_get(&pdev->dev, "ocmem");

	ret = IS_ERR(ocmem_icc_path);

	if (ret) {

		/* allow -ENODATA, ocmem icc is optional */

		if (ret != -ENODATA)

			goto fail;

		ocmem_icc_path = NULL;

	}





	/*

	 * Set the ICC path to maximum speed for now by multiplying the fastest

	 * frequency by the bus width (8). We'll want to scale this later on to

	 * improve battery life.

	 */

	icc_set_bw(gpu->icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(gpu->ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);



	return gpu;

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+18 −2
Original line number Diff line number Diff line
@@ -648,6 +648,8 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 
	struct msm_gpu *gpu;

	struct msm_drm_private *priv = dev->dev_private;

	struct platform_device *pdev = priv->gpu_pdev;

	struct icc_path *ocmem_icc_path;

	struct icc_path *icc_path;

	int ret;



	if (!pdev) {
@@ -694,13 +696,27 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 
		goto fail;

	}



	icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");

	ret = IS_ERR(icc_path);

	if (ret)

		goto fail;



	ocmem_icc_path = devm_of_icc_get(&pdev->dev, "ocmem");

	ret = IS_ERR(ocmem_icc_path);

	if (ret) {

		/* allow -ENODATA, ocmem icc is optional */

		if (ret != -ENODATA)

			goto fail;

		ocmem_icc_path = NULL;

	}



	/*

	 * Set the ICC path to maximum speed for now by multiplying the fastest

	 * frequency by the bus width (8). We'll want to scale this later on to

	 * improve battery life.

	 */

	icc_set_bw(gpu->icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(gpu->ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);

	icc_set_bw(ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);



	return gpu;

CRA Git | Maintained and supported by SUSTech CRA and CCSE