Commit 60f2b4b8 authored by Vineet Gupta's avatar Vineet Gupta
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ARC: [intc-compact] simplify code for 2 priority levels 



ARC700 support for 2 interrupt priorities historically allowed even slow
perpherals such as emac and uart to setup high priority interrupts
which was wrong from the beginning as they could possibly delay the more
critical timer interrupt.

The hardware support for 2 level interrupts in ARCompact is less than
ideal anyways (judging from the "hacks" in low level entry code and thus
is not used in productions systems I know of.

So reduce the scope of this to timer only, thereby reducing a bunch of
complexity.

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 49acadff

arch/arc/Kconfig

+2 −20
Original line number Diff line number Diff line
@@ -186,9 +186,6 @@ if SMP 
config ARC_HAS_COH_CACHES

	def_bool n



config ARC_HAS_REENTRANT_IRQ_LV2

	def_bool n



config ARC_MCIP

	bool "ARConnect Multicore IP (MCIP) Support "

	depends on ISA_ARCV2
@@ -366,25 +363,10 @@ config NODES_SHIFT 
if ISA_ARCOMPACT



config ARC_COMPACT_IRQ_LEVELS

	bool "ARCompact IRQ Priorities: High(2)/Low(1)"

	bool "Setup Timer IRQ as high Priority"

	default n

	# Timer HAS to be high priority, for any other high priority config

	select ARC_IRQ3_LV2

	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy

	depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2



if ARC_COMPACT_IRQ_LEVELS



config ARC_IRQ3_LV2

	bool



config ARC_IRQ5_LV2

	bool



config ARC_IRQ6_LV2

	bool



endif	#ARC_COMPACT_IRQ_LEVELS

	depends on !SMP



config ARC_FPU_SAVE_RESTORE

	bool "Enable FPU state persistence across context switch"

arch/arc/kernel/entry-compact.S

+2 −16
Original line number Diff line number Diff line
@@ -91,27 +91,13 @@ VECTOR mem_service ; 0x8, Mem exception (0x1) 
VECTOR   instr_service           ; 0x10, Instrn Error   (0x2)



; ******************** Device ISRs **********************

#ifdef CONFIG_ARC_IRQ3_LV2

VECTOR   handle_interrupt_level2

#else

VECTOR   handle_interrupt_level1

#endif



VECTOR   handle_interrupt_level1



#ifdef CONFIG_ARC_IRQ5_LV2

VECTOR   handle_interrupt_level2

#else

VECTOR   handle_interrupt_level1

#endif



#ifdef CONFIG_ARC_IRQ6_LV2

#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS

VECTOR   handle_interrupt_level2

#else

VECTOR   handle_interrupt_level1

#endif



.rept   25

.rept   28

VECTOR   handle_interrupt_level1 ; Other devices

.endr

arch/arc/kernel/intc-compact.c

+2 −4
Original line number Diff line number Diff line
@@ -28,10 +28,8 @@ void arc_init_IRQ(void) 
{

	int level_mask = 0;



       /* setup any high priority Interrupts (Level2 in ARCompact jargon) */

	level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;

	level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;

	level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;

       /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */

	level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;



	/*

	 * Write to register, even if no LV2 IRQs configured to reset it

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