Commit 60f1292f authored by Bruce Allan's avatar Bruce Allan Committed by David S. Miller
Browse files

e1000e: do not write SmartSpeed register bits on parts without support 



The driver was accessing register bits for features on parts that do
not support that feature.  This could cause problems in the hardware.

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fc0c7760

drivers/net/e1000e/ich8lan.c

+15 −4
Original line number Diff line number Diff line
@@ -977,12 +977,14 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 
		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;

		ew32(PHY_CTRL, phy_ctrl);



		if (phy->type != e1000_phy_igp_3)

			return 0;



		/*

		 * Call gig speed drop workaround on LPLU before accessing

		 * any PHY registers

		 */

		if ((hw->mac.type == e1000_ich8lan) &&

		    (hw->phy.type == e1000_phy_igp_3))

		if (hw->mac.type == e1000_ich8lan)

			e1000e_gig_downshift_workaround_ich8lan(hw);



		/* When LPLU is enabled, we should disable SmartSpeed */
@@ -995,6 +997,9 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 
		phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;

		ew32(PHY_CTRL, phy_ctrl);



		if (phy->type != e1000_phy_igp_3)

			return 0;



		/*

		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used

		 * during Dx states where the power conservation is most
@@ -1054,6 +1059,10 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 
	if (!active) {

		phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;

		ew32(PHY_CTRL, phy_ctrl);



		if (phy->type != e1000_phy_igp_3)

			return 0;



		/*

		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used

		 * during Dx states where the power conservation is most
@@ -1089,12 +1098,14 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 
		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;

		ew32(PHY_CTRL, phy_ctrl);



		if (phy->type != e1000_phy_igp_3)

			return 0;



		/*

		 * Call gig speed drop workaround on LPLU before accessing

		 * any PHY registers

		 */

		if ((hw->mac.type == e1000_ich8lan) &&

		    (hw->phy.type == e1000_phy_igp_3))

		if (hw->mac.type == e1000_ich8lan)

			e1000e_gig_downshift_workaround_ich8lan(hw);



		/* When LPLU is enabled, we should disable SmartSpeed */

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