Commit 60ef4b07 authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: imx6: Share PHY debug register definitions 



Both pcie-designware.c and pci-imx6.c contain custom definitions for
PHY debug registers R0/R1 and on top of that there's already a
definition for R0 in pcie-designware.h. Move all of the definitions to
pcie-designware.h. No functional change intended.

Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
parent 680728e4

drivers/pci/controller/dwc/pci-imx6.c

+2 −4
Original line number Diff line number Diff line
@@ -103,8 +103,6 @@ struct imx6_pcie { 


/* PCIe Port Logic registers (memory-mapped) */

#define PL_OFFSET 0x700

#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)

#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)



#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)

#define PCIE_PHY_CTRL_DATA_LOC 0
@@ -831,8 +829,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 


err_reset_phy:

	dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",

		dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),

		dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));

		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),

		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));

	imx6_pcie_reset_phy(imx6_pcie);

	return ret;

}

drivers/pci/controller/dwc/pcie-designware.c

+3 −9
Original line number Diff line number Diff line
@@ -14,12 +14,6 @@ 


#include "pcie-designware.h"



/* PCIe Port Logic registers */

#define PLR_OFFSET			0x700

#define PCIE_PHY_DEBUG_R1		(PLR_OFFSET + 0x2c)

#define PCIE_PHY_DEBUG_R1_LINK_UP	(0x1 << 4)

#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(0x1 << 29)



int dw_pcie_read(void __iomem *addr, int size, u32 *val)

{

	if (!IS_ALIGNED((uintptr_t)addr, size)) {
@@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci) 
	if (pci->ops->link_up)

		return pci->ops->link_up(pci);



	val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);

	return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&

		(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));

	val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);

	return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&

		(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));

}



void dw_pcie_setup(struct dw_pcie *pci)

drivers/pci/controller/dwc/pcie-designware.h

+3 −0
Original line number Diff line number Diff line
@@ -41,6 +41,9 @@ 
#define PCIE_PORT_DEBUG0		0x728

#define PORT_LOGIC_LTSSM_STATE_MASK	0x1f

#define PORT_LOGIC_LTSSM_STATE_L0	0x11

#define PCIE_PORT_DEBUG1		0x72C

#define PCIE_PORT_DEBUG1_LINK_UP		BIT(4)

#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING	BIT(29)



#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C

#define PORT_LOGIC_SPEED_CHANGE		BIT(17)

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