Commit 60c67382 authored Jun 25, 2013 by Brian Norris Committed by David Woodhouse Aug 05, 2013

mtd: nand: detect OOB size for Toshiba 24nm raw SLC



Toshiba NAND datasheets have not been very forthcoming on OOB size
information; they do not provide any bitfields in the ID string for
spare area. In their 24nm technology flash, however, Toshiba migrated
their NAND to have 32 bytes spare per 512 bytes of page area (up from
the traditional 16 bytes), as they now require 8-bit ECC or higher.

I have discussed this issue directly with Toshiba representatives, and
they acknowledge this problem. They recommend detecting these flash
based on their technology node as follows:

  For 24nm Toshiba SLC raw NAND (not BENAND -- Built-in Ecc NAND), there
  are 32 bytes of spare area for every 512 bytes of in-band data area.

We can implement this rule with the following snippet of a device ID
decode table, which applies to all their 43nm, 32nm, and 24nm SLC NAND
(this table is not fully in the NAND datasheets, but it was provided
directly by Toshiba representatives):

  - ID byte 5, bit[7]:
          1    -> BENAND
          0    -> raw SLC

  - ID byte 6, bits[2:0]:
          100b -> 43nm
          101b -> 32nm
          110b -> 24nm
          111b -> Reserved

I'm also working with Toshiba on including this bitfield description for
their 5th and 6th ID bytes in their public data sheets.

I will provide the 8-byte ID strings from the two 24nm Toshiba samples I
have; their first 6 bytes match the documentation I received from
Toshiba:

  24nm SLC 1Gbit TC58NVG0S3HTA00
  0x98 0xf1 0x80 0x15 0x72 0x16 0x08 0x00

  24nm SLC 2Gbit TC58NVG1S3HTA00
  0x98 0xda 0x90 0x15 0x76 0x16 0x08 0x00

I have also tested for regressions with:

  43nm SLC 4Gbit TC58NVG2S3ETA00
  0x98 0xdc 0x90 0x15 0x76 0x14 0x03 0x10

  32nm SLC 8Gbit TC58NVG3SOFA00
  0x98 0xd3 0x90 0x26 0x76 0x15 0x02 0x08

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

parent fe2f4c8e

drivers/mtd/nand/nand_base.c

+16 −0

Original line number	Diff line number	Diff line
		@@ -3081,6 +3081,22 @@ static void nand_decode_ext_id(struct mtd_info mtd, struct nand_chip chip,
		extid >>= 2;
		/* Get buswidth information */
		*busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;

		/*
		* Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
		* 512B page. For Toshiba SLC, we decode the 5th/6th byte as
		* follows:
		* - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
		* 110b -> 24nm
		* - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
		*/
		if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
		!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
		(id_data[5] & 0x7) == 0x6 /* 24nm */ &&
		!(id_data[4] & 0x80) /* !BENAND */) {
		mtd->oobsize = 32 * mtd->writesize >> 9;
		}

		}
		}

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