Commit 60baf75e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.21-tag2' of... 

Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for CPEX (timer) clocks on various R-Car Gen3 and RZ/G2 SoCs
 - Add support for SDHI HS400 clocks on early revisions of R-Car H3 and M3-W
 - Miscellaneous fixes based on the Hardware Manual Errata

* tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
  clk: renesas: rcar-gen3: Add documentation for SD clocks
  clk: renesas: rcar-gen3: Set state when registering SD clocks
  clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
  clk: renesas: r8a77995: Add missing CPEX clock
  clk: renesas: r8a77995: Remove non-existent SSP clocks
  clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
  clk: renesas: r8a77995: Correct parent clock of DU
  clk: renesas: r8a77990: Correct parent clock of DU
  clk: renesas: r8a77970: Add CPEX clock
  clk: renesas: r8a77965: Add CPEX clock
  clk: renesas: r8a7796: Add CPEX clock
  clk: renesas: r8a7795: Add CPEX clock
  clk: renesas: r8a774a1: Add CPEX clock
  dt-bindings: clock: r8a7796: Remove CSIREF clock
  dt-bindings: clock: r8a7795: Remove CSIREF clock
parents 1ef06003 36c4da4f

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 


	DEF_FIXED("cl",         R8A774A1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A774A1_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A774A1_CLK_CPEX,  CLK_EXTAL,      2, 1),



	DEF_DIV6P1("csi0",      R8A774A1_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),

	DEF_DIV6P1("mso",       R8A774A1_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cr",         R8A7795_CLK_CR,    CLK_PLL1_DIV4,  2, 1),

	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A7795_CLK_CPEX,  CLK_EXTAL,      2, 1),



	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

	DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 


	DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A7796_CLK_CPEX,  CLK_EXTAL,      2, 1),



	DEF_DIV6P1("canfd",     R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

	DEF_DIV6P1("csi0",      R8A7796_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { 


	DEF_FIXED("cl",		R8A77965_CLK_CL,	CLK_PLL1_DIV2,	48, 1),

	DEF_FIXED("cp",		R8A77965_CLK_CP,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cpex",	R8A77965_CLK_CPEX,	CLK_EXTAL,	2, 1),



	DEF_DIV6P1("canfd",	R8A77965_CLK_CANFD,	CLK_PLL1_DIV4,	0x244),

	DEF_DIV6P1("csi0",	R8A77965_CLK_CSI0,	CLK_PLL1_DIV4,	0x00c),

drivers/clk/renesas/r8a77970-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { 


	DEF_FIXED("cl",		R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",		R8A77970_CLK_CP,    CLK_EXTAL,	    2, 1),

	DEF_FIXED("cpex",	R8A77970_CLK_CPEX,  CLK_EXTAL,	    2, 1),



	DEF_DIV6P1("canfd",	R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

	DEF_DIV6P1("mso",	R8A77970_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

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