Commit 60a10650 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2020-08-24' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



Some fixes for v5.9 plus the one opp/bandwidth scaling patch ("drm:
msm: a6xx: use dev_pm_opp_set_bw to scale DDR") which was not included
in the initial pull due to dependency on patch landing thru OPP tree

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ <CAF6AEGt45A4ObyhEdC5Ga4f4cAf-NBSVRECu7df3Gh6-X4G3tQ@mail.gmail.com
parents 6284a418 5e0c22d4

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+29 −9
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) 


	if (!gmu->legacy) {

		a6xx_hfi_set_freq(gmu, perf_index);

		icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));

		dev_pm_opp_set_bw(&gpu->pdev->dev, opp);

		pm_runtime_put(gmu->dev);

		return;

	}
@@ -157,11 +157,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) 
	if (ret)

		dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);



	/*

	 * Eventually we will want to scale the path vote with the frequency but

	 * for now leave it at max so that the performance is nominal.

	 */

	icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));

	dev_pm_opp_set_bw(&gpu->pdev->dev, opp);

	pm_runtime_put(gmu->dev);

}
@@ -204,6 +200,16 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) 
{

	int ret;

	u32 val;

	u32 mask, reset_val;



	val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);

	if (val <= 0x20010004) {

		mask = 0xffffffff;

		reset_val = 0xbabeface;

	} else {

		mask = 0x1ff;

		reset_val = 0x100;

	}



	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
@@ -215,7 +221,7 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) 
	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);



	ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,

		val == 0xbabeface, 100, 10000);

		(val & mask) == reset_val, 100, 10000);



	if (ret)

		DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
@@ -845,10 +851,24 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 
	if (IS_ERR_OR_NULL(gpu_opp))

		return;



	gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */

	a6xx_gmu_set_freq(gpu, gpu_opp);

	dev_pm_opp_put(gpu_opp);

}



static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)

{

	struct dev_pm_opp *gpu_opp;

	unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];



	gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);

	if (IS_ERR_OR_NULL(gpu_opp))

		return;



	dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp);

	dev_pm_opp_put(gpu_opp);

}



int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)

{

	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
@@ -882,7 +902,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 
	}



	/* Set the bus quota to a reasonable value for boot */

	icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072));

	a6xx_gmu_set_initial_bw(gpu, gmu);



	/* Enable the GMU interrupt */

	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
@@ -1051,7 +1071,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 
		a6xx_gmu_shutdown(gmu);



	/* Remove the bus vote */

	icc_set_bw(gpu->icc_path, 0, 0);

	dev_pm_opp_set_bw(&gpu->pdev->dev, NULL);



	/*

	 * Make sure the GX domain is off before turning off the GMU (CX)

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+2 −1
Original line number Diff line number Diff line
@@ -938,6 +938,7 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) 
		msm_gem_kernel_put(dumper.bo, gpu->aspace, true);

	}



	if (snapshot_debugbus)

		a6xx_get_debugbus(gpu, a6xx_state);



	return  &a6xx_state->base;

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+1 −1
Original line number Diff line number Diff line
@@ -372,7 +372,7 @@ static const struct a6xx_indexed_registers { 
	u32 data;

	u32 count;

} a6xx_indexed_reglist[] = {

	{ "CP_SEQ_STAT", REG_A6XX_CP_SQE_STAT_ADDR,

	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,

		REG_A6XX_CP_SQE_STAT_DATA, 0x33 },

	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,

		REG_A6XX_CP_DRAW_STATE_DATA, 0x100 },

drivers/gpu/drm/msm/adreno/adreno_device.c

+4 −0
Original line number Diff line number Diff line
@@ -14,6 +14,10 @@ bool hang_debug = false; 
MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");

module_param_named(hang_debug, hang_debug, bool, 0600);



bool snapshot_debugbus = false;

MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");

module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);



static const struct adreno_info gpulist[] = {

	{

		.rev   = ADRENO_REV(2, 0, 0, 0),

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -396,7 +396,7 @@ int adreno_hw_init(struct msm_gpu *gpu) 
		ring->next = ring->start;



		/* reset completed fence seqno: */

		ring->memptrs->fence = ring->seqno;

		ring->memptrs->fence = ring->fctx->completed_fence;

		ring->memptrs->rptr = 0;

	}

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