Commit 60658f8a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: 6524/1: GIC irq desciptor bug fix
  ARM: 6523/1: iop: ensure sched_clock() is notrace
  ARM: 6456/1: Fix for building DEBUG with sa11xx_base.c as a module.
  ARM: 6519/1: kuser: Fix incorrect cmpxchg syscall in kuser helpers
  ARM: 6505/1: kprobes: Don't HAVE_KPROBES when CONFIG_THUMB2_KERNEL is selected
  ARM: 6508/1: vexpress: Correct data alignment in headsmp.S for CONFIG_THUMB2_KERNEL
  ARM: 6507/1: RealView: Correct data alignment in headsmp.S for CONFIG_THUMB2_KERNEL
  ARM: 6504/1: Thumb-2: Fix long-distance conditional branches in head.S for Thumb-2.
  ARM: 6503/1: Thumb-2: Restore sensible zImage header layout for CONFIG_THUMB2_KERNEL
  ARM: 6502/1: Thumb-2: Fix CONFIG_THUMB2_KERNEL breakage in compressed/head.S
  ARM: 6501/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in mm/proc-v7.S
  ARM: 6500/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in kernel/head.S
  ARM: 6499/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in bootp/init.S
  ARM: 6498/1: vfp: Correct data alignment for CONFIG_THUMB2_KERNEL
  ARM: 6497/1: kexec: Correct data alignment for CONFIG_THUMB2_KERNEL
  ARM: 6496/1: GIC: Do not try to register more then NR_IRQS interrupts
  ARM: cns3xxx: Fix build with CONFIG_PCI=y
parents 771f8bc7 f444a57c

arch/arm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ config ARM 
	select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)

	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)

	select HAVE_ARCH_KGDB

	select HAVE_KPROBES if (!XIP_KERNEL)

	select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)

	select HAVE_KRETPROBES if (HAVE_KPROBES)

	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)

	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)

arch/arm/boot/Makefile

+0 −5
Original line number Diff line number Diff line
@@ -70,12 +70,7 @@ else 
$(obj)/uImage: LOADADDR=$(ZRELADDR)

endif



ifeq ($(CONFIG_THUMB2_KERNEL),y)

# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode

$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")

else

$(obj)/uImage: STARTADDR=$(LOADADDR)

endif



$(obj)/uImage:	$(obj)/zImage FORCE

	$(call if_changed,uimage)

arch/arm/boot/bootp/init.S

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ move: ldmia r4!, {r7 - r10} @ move 32-bytes at a time 


		.size	_start, . - _start



		.align



		.type	data,#object

data:		.word	initrd_start		@ source initrd address

		.word	initrd_phys		@ destination initrd address

arch/arm/boot/compressed/head.S

+10 −3
Original line number Diff line number Diff line
@@ -125,9 +125,13 @@ wait: mrc p14, 0, pc, c0, c1, 0 
 * sort out different calling conventions

 */

		.align

		.arm				@ Always enter in ARM state

start:

		.type	start,#function

		.rept	8

 THUMB(		adr	r12, BSYM(1f)	)

 THUMB(		bx	r12		)

 THUMB(		.rept	6		)

 ARM(		.rept	8		)

		mov	r0, r0

		.endr
@@ -135,6 +139,7 @@ start: 
		.word	0x016f2818		@ Magic numbers to help the loader

		.word	start			@ absolute load/run zImage address

		.word	_edata			@ zImage end address

 THUMB(		.thumb			)

1:		mov	r7, r1			@ save architecture ID

		mov	r8, r2			@ save atags pointer
@@ -174,7 +179,8 @@ not_angel: 
		ldr	sp, [r0, #28]

#ifdef CONFIG_AUTO_ZRELADDR

		@ determine final kernel image address

		and	r4, pc, #0xf8000000

		mov	r4, pc

		and	r4, r4, #0xf8000000

		add	r4, r4, #TEXT_OFFSET

#else

		ldr	r4, =zreladdr
@@ -445,7 +451,8 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size 
 */

		mov	r1, #0x1e

		orr	r1, r1, #3 << 10

		mov	r2, pc, lsr #20

		mov	r2, pc

		mov	r2, r2, lsr #20

		orr	r1, r1, r2, lsl #20

		add	r0, r3, r2, lsl #2

		str	r1, [r0], #4

arch/arm/common/gic.c

+24 −16
Original line number Diff line number Diff line
@@ -146,9 +146,15 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) 
	unsigned int shift = (irq % 4) * 8;

	unsigned int cpu = cpumask_first(mask_val);

	u32 val;

	struct irq_desc *desc;



	spin_lock(&irq_controller_lock);

	irq_desc[irq].node = cpu;

	desc = irq_to_desc(irq);

	if (desc == NULL) {

		spin_unlock(&irq_controller_lock);

		return -EINVAL;

	}

	desc->node = cpu;

	val = readl(reg) & ~(0xff << shift);

	val |= 1 << (cpu + shift);

	writel(val, reg);
@@ -210,7 +216,7 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 
void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,

			  unsigned int irq_start)

{

	unsigned int max_irq, i;

	unsigned int gic_irqs, irq_limit, i;

	u32 cpumask = 1 << smp_processor_id();



	if (gic_nr >= MAX_GIC_NR)
@@ -226,47 +232,49 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, 


	/*

	 * Find out how many interrupts are supported.

	 */

	max_irq = readl(base + GIC_DIST_CTR) & 0x1f;

	max_irq = (max_irq + 1) * 32;



	/*

	 * The GIC only supports up to 1020 interrupt sources.

	 * Limit this to either the architected maximum, or the

	 * platform maximum.

	 */

	if (max_irq > max(1020, NR_IRQS))

		max_irq = max(1020, NR_IRQS);

	gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;

	gic_irqs = (gic_irqs + 1) * 32;

	if (gic_irqs > 1020)

		gic_irqs = 1020;



	/*

	 * Set all global interrupts to be level triggered, active low.

	 */

	for (i = 32; i < max_irq; i += 16)

	for (i = 32; i < gic_irqs; i += 16)

		writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);



	/*

	 * Set all global interrupts to this CPU only.

	 */

	for (i = 32; i < max_irq; i += 4)

	for (i = 32; i < gic_irqs; i += 4)

		writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);



	/*

	 * Set priority on all global interrupts.

	 */

	for (i = 32; i < max_irq; i += 4)

	for (i = 32; i < gic_irqs; i += 4)

		writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);



	/*

	 * Disable all interrupts.  Leave the PPI and SGIs alone

	 * as these enables are banked registers.

	 */

	for (i = 32; i < max_irq; i += 32)

	for (i = 32; i < gic_irqs; i += 32)

		writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);



	/*

	 * Limit number of interrupts registered to the platform maximum

	 */

	irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;

	if (WARN_ON(irq_limit > NR_IRQS))

		irq_limit = NR_IRQS;



	/*

	 * Setup the Linux IRQ subsystem.

	 */

	for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {

	for (i = irq_start; i < irq_limit; i++) {

		set_irq_chip(i, &gic_chip);

		set_irq_chip_data(i, &gic_data[gic_nr]);

		set_irq_handler(i, handle_level_irq);

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