mailbox: mediatek: cmdq: clear the event in cmdq initial flow (6058f118) · Commits · 戴 / test

GCE hardware stored event information in own internal sysram, if the initial value in those sysram is not zero value it will cause a situation that gce can wait the event immediately after client ask gce to wait event but not really trigger the corresponding hardware. In order to make sure that the wait event function is exactly correct, we need to clear the sysram value in cmdq initial flow. Fixes: ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by:

Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by:

CK Hu <ck.hu@mediatek.com> Reviewed-by:

Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:

Jassi Brar <jaswinder.singh@linaro.org>

drivers/mailbox/mtk-cmdq-mailbox.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -21,6 +21,7 @@
		#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)

		#define CMDQ_CURR_IRQ_STATUS 0x10
		#define CMDQ_SYNC_TOKEN_UPDATE 0x68
		#define CMDQ_THR_SLOT_CYCLES 0x30
		#define CMDQ_THR_BASE 0x100
		#define CMDQ_THR_SIZE 0x80
		@@ -104,8 +105,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread)

		static void cmdq_init(struct cmdq *cmdq)
		{
		int i;

		WARN_ON(clk_enable(cmdq->clock) < 0);
		writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
		for (i = 0; i <= CMDQ_MAX_EVENT; i++)
		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
		clk_disable(cmdq->clock);
		}

include/linux/mailbox/mtk-cmdq-mailbox.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,9 @@
		#define CMDQ_WFE_WAIT BIT(15)
		#define CMDQ_WFE_WAIT_VALUE 0x1

		/** cmdq event maximum */
		#define CMDQ_MAX_EVENT 0x3ff

		/*
		* CMDQ_CODE_MASK:
		* set write mask

include/linux/soc/mediatek/mtk-cmdq.h

+0 −3

Original line number	Diff line number	Diff line
		@@ -13,9 +13,6 @@

		#define CMDQ_NO_TIMEOUT 0xffffffffu

		/** cmdq event maximum */
		#define CMDQ_MAX_EVENT 0x3ff

		struct cmdq_pkt;

		struct cmdq_client {

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