Commit 6057317c authored by Jyri Sarha's avatar Jyri Sarha
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dt-bindings: display: ti,j721e-dss: Add dt-schema yaml binding 



Add dt-schema yaml bindig for J721E DSS, J721E version TI Keystone
Display SubSystem.

Version history:

v2: no change

v3: - reg-names: "wp" -> "wb"
    - Add ports node
    - Add includes to dts example
    - reindent dts example

v4: - Add descriptions to reg, clocks, and interrupts properties
    - Remove minItems when its value is the same as maxItems value

v5: - itemize reg, clocks and interrupts properties' descriptions
    - there is no "vp" reg-name, only "wb" for write back

v6: - Add Reviewed-by: from Rob Herring <robh@kernel.org> and
      Benoit Parrot <bparrot@ti.com>

v7: no change

v8: no change

v9: no change

Signed-off-by: default avatarJyri Sarha <jsarha@ti.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarBenoit Parrot <bparrot@ti.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fcba52837808853a4b2bf729bd33bd986cbdadf4.1580129724.git.jsarha@ti.com
parent 2d8730f1

Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml

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+208 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 Texas Instruments Incorporated

%YAML 1.2

---

$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Texas Instruments J721E Display Subsystem



maintainers:

  - Jyri Sarha <jsarha@ti.com>

  - Tomi Valkeinen <tomi.valkeinen@ti.com>



description: |

  The J721E TI Keystone Display SubSystem with four output ports and

  four video planes. There is two full video planes and two "lite

  planes" without scaling support. The video ports can be connected to

  the SoC's DPI pins or to integrated display bridges on the SoC.



properties:

  compatible:

    const: ti,j721e-dss



  reg:

    items:

      - description: common_m DSS Master common

      - description: common_s0 DSS Shared common 0

      - description: common_s1 DSS Shared common 1

      - description: common_s2 DSS Shared common 2

      - description: VIDL1 light video plane 1

      - description: VIDL2 light video plane 2

      - description: VID1 video plane 1

      - description: VID1 video plane 2

      - description: OVR1 overlay manager for vp1

      - description: OVR2 overlay manager for vp2

      - description: OVR3 overlay manager for vp3

      - description: OVR4 overlay manager for vp4

      - description: VP1 video port 1

      - description: VP2 video port 2

      - description: VP3 video port 3

      - description: VP4 video port 4

      - description: WB Write Back



  reg-names:

    items:

      - const: common_m

      - const: common_s0

      - const: common_s1

      - const: common_s2

      - const: vidl1

      - const: vidl2

      - const: vid1

      - const: vid2

      - const: ovr1

      - const: ovr2

      - const: ovr3

      - const: ovr4

      - const: vp1

      - const: vp2

      - const: vp3

      - const: vp4

      - const: wb



  clocks:

    items:

      - description: fck DSS functional clock

      - description: vp1 Video Port 1 pixel clock

      - description: vp2 Video Port 2 pixel clock

      - description: vp3 Video Port 3 pixel clock

      - description: vp4 Video Port 4 pixel clock



  clock-names:

    items:

      - const: fck

      - const: vp1

      - const: vp2

      - const: vp3

      - const: vp4



  interrupts:

     items:

      - description: common_m DSS Master common

      - description: common_s0 DSS Shared common 0

      - description: common_s1 DSS Shared common 1

      - description: common_s2 DSS Shared common 2



  interrupt-names:

    items:

      - const: common_m

      - const: common_s0

      - const: common_s1

      - const: common_s2



  power-domains:

    maxItems: 1

    description: phandle to the associated power domain



  ports:

    type: object

    description:

      Ports as described in Documentation/devictree/bindings/graph.txt

    properties:

      "#address-cells":

        const: 1



      "#size-cells":

        const: 0



      port@0:

        type: object

        description:

          The output port node form video port 1



      port@1:

        type: object

        description:

          The output port node from video port 2



      port@2:

        type: object

        description:

          The output port node from video port 3



      port@3:

        type: object

        description:

          The output port node from video port 4



    required:

      - "#address-cells"

      - "#size-cells"



  max-memory-bandwidth:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Input memory (from main memory to dispc) bandwidth limit in

      bytes per second



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - ports



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/soc/ti,sci_pm_domain.h>



    dss: dss@04a00000 {

            compatible = "ti,j721e-dss";

            reg =   <0x00 0x04a00000 0x00 0x10000>, /* common_m */

                    <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/

                    <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/

                    <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/

                    <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */

                    <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */

                    <0x00 0x04a50000 0x00 0x10000>, /* vid1 */

                    <0x00 0x04a60000 0x00 0x10000>, /* vid2 */

                    <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */

                    <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */

                    <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */

                    <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */

                    <0x00 0x04a80000 0x00 0x10000>, /* vp1 */

                    <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */

                    <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */

                    <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */

                    <0x00 0x04af0000 0x00 0x10000>; /* wb */

            reg-names = "common_m", "common_s0",

                    "common_s1", "common_s2",

                    "vidl1", "vidl2","vid1","vid2",

                    "ovr1", "ovr2", "ovr3", "ovr4",

                    "vp1", "vp2", "vp3", "vp4",

                    "wb";

            clocks =        <&k3_clks 152 0>,

                            <&k3_clks 152 1>,

                            <&k3_clks 152 4>,

                            <&k3_clks 152 9>,

                            <&k3_clks 152 13>;

            clock-names = "fck", "vp1", "vp2", "vp3", "vp4";

            power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;

            interrupts =    <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,

                            <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,

                            <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,

                            <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names =       "common_m",

                                    "common_s0",

                                    "common_s1",

                                    "common_s2";

            ports {

                    #address-cells = <1>;

                    #size-cells = <0>;

                    port@0 {

                            reg = <0>;



                            dpi_out_0: endpoint {

                                    remote-endpoint = <&dp_bridge_input>;

                            };

                    };

            };

    };

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