Commit 604234f3 authored by Jordan Crouse's avatar Jordan Crouse Committed by Rob Clark
Browse files

drm/msm: Enable expanded apriv support for a650 



a650 supports expanded apriv support that allows us to map critical buffers
(ringbuffer and memstore) as as privileged to protect them from corruption.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 34221545

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+5 −1
Original line number Diff line number Diff line
@@ -678,7 +678,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) 
			A6XX_PROTECT_RDONLY(0x980, 0x4));

	gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));



	if (adreno_is_a650(adreno_gpu)) {

	/* Enable expanded apriv for targets that support it */

	if (gpu->hw_apriv) {

		gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,

			(1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));

	}
@@ -1056,6 +1057,9 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 
	adreno_gpu->registers = NULL;

	adreno_gpu->reg_offsets = a6xx_register_offsets;



	if (adreno_is_a650(adreno_gpu))

		adreno_gpu->base.hw_apriv = true;



	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);

	if (ret) {

		a6xx_destroy(&(a6xx_gpu->base.base));

drivers/gpu/drm/msm/msm_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -908,7 +908,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 


	memptrs = msm_gem_kernel_new(drm,

		sizeof(struct msm_rbmemptrs) * nr_rings,

		MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,

		check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,

		&memptrs_iova);



	if (IS_ERR(memptrs)) {

drivers/gpu/drm/msm/msm_gpu.h

+11 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include "msm_drv.h"

#include "msm_fence.h"

#include "msm_ringbuffer.h"

#include "msm_gem.h"



struct msm_gem_submit;

struct msm_gpu_perfcntr;
@@ -139,6 +140,8 @@ struct msm_gpu { 
	} devfreq;



	struct msm_gpu_state *crashstate;

	/* True if the hardware supports expanded apriv (a650 and newer) */

	bool hw_apriv;

};



/* It turns out that all targets use the same ringbuffer size */
@@ -327,4 +330,12 @@ static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) 
	mutex_unlock(&gpu->dev->struct_mutex);

}



/*

 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can

 * support expanded privileges

 */

#define check_apriv(gpu, flags) \

	(((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))





#endif /* __MSM_GPU_H__ */

drivers/gpu/drm/msm/msm_ringbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -27,8 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, 
	ring->id = id;



	ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,

		MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,

		&ring->iova);

		check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),

		gpu->aspace, &ring->bo, &ring->iova);



	if (IS_ERR(ring->start)) {

		ret = PTR_ERR(ring->start);

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