Commit 602b9ba2 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'power' of git://github.com/hzhuang1/linux into next/pm 

* 'power' of git://github.com/hzhuang1/linux

:
  ARM: mmp: add pm support for pxa910
  ARM: mmp: ttc_dkb: add PMIC support
  ARM: cache: tauros2: add disable and resume callback
  ARM: mm: proc-mohawk: add suspend resume for mohawk
  ARM: mmp: add PM support for mmp2
  ARM: mmp: move XX_REG definition to addr-map.h

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 853b2039 902ca229

arch/arm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -2275,7 +2275,7 @@ source "kernel/power/Kconfig" 
config ARCH_SUSPEND_POSSIBLE

	depends on !ARCH_S5PC100

	depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \

		CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE

		CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK

	def_bool y



config ARM_CPU_SUSPEND

arch/arm/mach-mmp/Makefile

+5 −0
Original line number Diff line number Diff line
@@ -9,6 +9,11 @@ obj-$(CONFIG_CPU_PXA168) += pxa168.o 
obj-$(CONFIG_CPU_PXA910)	+= pxa910.o

obj-$(CONFIG_CPU_MMP2)		+= mmp2.o sram.o



ifeq ($(CONFIG_PM),y)

obj-$(CONFIG_CPU_PXA910)	+= pm-pxa910.o

obj-$(CONFIG_CPU_MMP2)		+= pm-mmp2.o

endif



# board support

obj-$(CONFIG_MACH_ASPENITE)	+= aspenite.o

obj-$(CONFIG_MACH_ZYLONITE2)	+= aspenite.o

arch/arm/mach-mmp/include/mach/addr-map.h

+12 −0
Original line number Diff line number Diff line
@@ -31,4 +31,16 @@ 
#define SMC_CS1_PHYS_BASE	0x90000000

#define SMC_CS1_PHYS_SIZE	0x10000000



#define APMU_VIRT_BASE		(AXI_VIRT_BASE + 0x82800)

#define APMU_REG(x)		(APMU_VIRT_BASE + (x))



#define APBC_VIRT_BASE		(APB_VIRT_BASE + 0x015000)

#define APBC_REG(x)		(APBC_VIRT_BASE + (x))



#define MPMU_VIRT_BASE		(APB_VIRT_BASE + 0x50000)

#define MPMU_REG(x)		(MPMU_VIRT_BASE + (x))



#define CIU_VIRT_BASE		(AXI_VIRT_BASE + 0x82c00)

#define CIU_REG(x)		(CIU_VIRT_BASE + (x))



#endif /* __ASM_MACH_ADDR_MAP_H */

arch/arm/mach-mmp/include/mach/pm-mmp2.h

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+61 −0
Original line number Diff line number Diff line 
/*

 * MMP2 Power Management Routines

 *

 * This software program is licensed subject to the GNU General Public License

 * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html

 *

 * (C) Copyright 2010 Marvell International Ltd.

 * All Rights Reserved

 */



#ifndef __MMP2_PM_H__

#define __MMP2_PM_H__



#include <mach/addr-map.h>



#define APMU_PJ_IDLE_CFG			APMU_REG(0x018)

#define APMU_PJ_IDLE_CFG_PJ_IDLE		(1 << 1)

#define APMU_PJ_IDLE_CFG_PJ_PWRDWN		(1 << 5)

#define APMU_PJ_IDLE_CFG_PWR_SW(x)		((x) << 16)

#define APMU_PJ_IDLE_CFG_L2_PWR_SW		(1 << 19)

#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK	(3 << 28)



#define APMU_SRAM_PWR_DWN			APMU_REG(0x08c)



#define MPMU_SCCR				MPMU_REG(0x038)

#define MPMU_PCR_PJ				MPMU_REG(0x1000)

#define MPMU_PCR_PJ_AXISD			(1 << 31)

#define MPMU_PCR_PJ_SLPEN			(1 << 29)

#define MPMU_PCR_PJ_SPSD			(1 << 28)

#define MPMU_PCR_PJ_DDRCORSD			(1 << 27)

#define MPMU_PCR_PJ_APBSD			(1 << 26)

#define MPMU_PCR_PJ_INTCLR			(1 << 24)

#define MPMU_PCR_PJ_SLPWP0			(1 << 23)

#define MPMU_PCR_PJ_SLPWP1			(1 << 22)

#define MPMU_PCR_PJ_SLPWP2			(1 << 21)

#define MPMU_PCR_PJ_SLPWP3			(1 << 20)

#define MPMU_PCR_PJ_VCTCXOSD			(1 << 19)

#define MPMU_PCR_PJ_SLPWP4			(1 << 18)

#define MPMU_PCR_PJ_SLPWP5			(1 << 17)

#define MPMU_PCR_PJ_SLPWP6			(1 << 16)

#define MPMU_PCR_PJ_SLPWP7			(1 << 15)



#define MPMU_PLL2_CTRL1				MPMU_REG(0x0414)

#define MPMU_CGR_PJ				MPMU_REG(0x1024)

#define MPMU_WUCRM_PJ				MPMU_REG(0x104c)

#define MPMU_WUCRM_PJ_WAKEUP(x)			(1 << (x))

#define MPMU_WUCRM_PJ_RTC_ALARM			(1 << 17)



enum {

	POWER_MODE_ACTIVE = 0,

	POWER_MODE_CORE_INTIDLE,

	POWER_MODE_CORE_EXTIDLE,

	POWER_MODE_APPS_IDLE,

	POWER_MODE_APPS_SLEEP,

	POWER_MODE_CHIP_SLEEP,

	POWER_MODE_SYS_SLEEP,

};



extern void mmp2_pm_enter_lowpower_mode(int state);

extern int mmp2_set_wake(struct irq_data *d, unsigned int on);

#endif

arch/arm/mach-mmp/include/mach/pm-pxa910.h

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+77 −0
Original line number Diff line number Diff line 
/*

 * PXA910 Power Management Routines

 *

 * This software program is licensed subject to the GNU General Public License

 * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html

 *

 * (C) Copyright 2009 Marvell International Ltd.

 * All Rights Reserved

 */



#ifndef __PXA910_PM_H__

#define __PXA910_PM_H__



#define APMU_MOH_IDLE_CFG			APMU_REG(0x0018)

#define APMU_MOH_IDLE_CFG_MOH_IDLE		(1 << 1)

#define APMU_MOH_IDLE_CFG_MOH_PWRDWN		(1 << 5)

#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN	(1 << 6)

#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x)		(((x) & 0x3) << 16)

#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x)	(((x) & 0x3) << 18)

#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ	(1 << 21)

#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN	(1 << 20)



#define APMU_SQU_CLK_GATE_CTRL			APMU_REG(0x001c)

#define APMU_MC_HW_SLP_TYPE			APMU_REG(0x00b0)



#define MPMU_FCCR				MPMU_REG(0x0008)

#define MPMU_APCR				MPMU_REG(0x1000)

#define MPMU_APCR_AXISD				(1 << 31)

#define MPMU_APCR_DSPSD				(1 << 30)

#define MPMU_APCR_SLPEN				(1 << 29)

#define MPMU_APCR_DTCMSD			(1 << 28)

#define MPMU_APCR_DDRCORSD			(1 << 27)

#define MPMU_APCR_APBSD				(1 << 26)

#define MPMU_APCR_BBSD				(1 << 25)

#define MPMU_APCR_SLPWP0			(1 << 23)

#define MPMU_APCR_SLPWP1			(1 << 22)

#define MPMU_APCR_SLPWP2			(1 << 21)

#define MPMU_APCR_SLPWP3			(1 << 20)

#define MPMU_APCR_VCTCXOSD			(1 << 19)

#define MPMU_APCR_SLPWP4			(1 << 18)

#define MPMU_APCR_SLPWP5			(1 << 17)

#define MPMU_APCR_SLPWP6			(1 << 16)

#define MPMU_APCR_SLPWP7			(1 << 15)

#define MPMU_APCR_MSASLPEN			(1 << 14)

#define MPMU_APCR_STBYEN			(1 << 13)



#define MPMU_AWUCRM				MPMU_REG(0x104c)

#define MPMU_AWUCRM_AP_ASYNC_INT		(1 << 25)

#define MPMU_AWUCRM_AP_FULL_IDLE		(1 << 24)

#define MPMU_AWUCRM_SDH1			(1 << 23)

#define MPMU_AWUCRM_SDH2			(1 << 22)

#define MPMU_AWUCRM_KEYPRESS			(1 << 21)

#define MPMU_AWUCRM_TRACKBALL			(1 << 20)

#define MPMU_AWUCRM_NEWROTARY			(1 << 19)

#define MPMU_AWUCRM_RTC_ALARM			(1 << 17)

#define MPMU_AWUCRM_AP2_TIMER_3			(1 << 13)

#define MPMU_AWUCRM_AP2_TIMER_2			(1 << 12)

#define MPMU_AWUCRM_AP2_TIMER_1			(1 << 11)

#define MPMU_AWUCRM_AP1_TIMER_3			(1 << 10)

#define MPMU_AWUCRM_AP1_TIMER_2			(1 << 9)

#define MPMU_AWUCRM_AP1_TIMER_1			(1 << 8)

#define MPMU_AWUCRM_WAKEUP(x)			(1 << ((x) & 0x7))



enum {

	POWER_MODE_ACTIVE = 0,

	POWER_MODE_CORE_INTIDLE,

	POWER_MODE_CORE_EXTIDLE,

	POWER_MODE_APPS_IDLE,

	POWER_MODE_APPS_SLEEP,

	POWER_MODE_SYS_SLEEP,

	POWER_MODE_HIBERNATE,

	POWER_MODE_UDR,

};



extern int pxa910_set_wake(struct irq_data *data, unsigned int on);



#endif

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