Commit 5fe858b5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://github.com/davem330/sparc 

* git://github.com/davem330/sparc:
  sparc64: Force the execute bit in OpenFirmware's translation entries.
  sparc: Make '-p' boot option meaningful again.
  sparc, exec: remove redundant addr_limit assignment
  sparc64: Future proof Niagara cpu detection.
parents 8e8e500f f4142cba

arch/sparc/include/asm/spitfire.h

+2 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
#define SUN4V_CHIP_NIAGARA1	0x01

#define SUN4V_CHIP_NIAGARA2	0x02

#define SUN4V_CHIP_NIAGARA3	0x03

#define SUN4V_CHIP_NIAGARA4	0x04

#define SUN4V_CHIP_NIAGARA5	0x05

#define SUN4V_CHIP_UNKNOWN	0xff



#ifndef __ASSEMBLY__

arch/sparc/include/asm/xor_64.h

+3 −1
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = { 
	((tlb_type == hypervisor && \

	  (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \

	   sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \

	 &xor_block_niagara : \

	 &xor_block_VIS)

arch/sparc/kernel/cpu.c

+12 −0
Original line number Diff line number Diff line
@@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void) 
		sparc_pmu_type = "niagara3";

		break;



	case SUN4V_CHIP_NIAGARA4:

		sparc_cpu_type = "UltraSparc T4 (Niagara4)";

		sparc_fpu_type = "UltraSparc T4 integrated FPU";

		sparc_pmu_type = "niagara4";

		break;



	case SUN4V_CHIP_NIAGARA5:

		sparc_cpu_type = "UltraSparc T5 (Niagara5)";

		sparc_fpu_type = "UltraSparc T5 integrated FPU";

		sparc_pmu_type = "niagara5";

		break;



	default:

		printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",

		       prom_cpu_compatible);

arch/sparc/kernel/cpumap.c

+2 −0
Original line number Diff line number Diff line
@@ -325,6 +325,8 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index) 
	case SUN4V_CHIP_NIAGARA1:

	case SUN4V_CHIP_NIAGARA2:

	case SUN4V_CHIP_NIAGARA3:

	case SUN4V_CHIP_NIAGARA4:

	case SUN4V_CHIP_NIAGARA5:

		rover_inc_table = niagara_iterate_method;

		break;

	default:

arch/sparc/kernel/head_64.S

+22 −3
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ prom_sun4v_name: 
prom_niagara_prefix:

	.asciz	"SUNW,UltraSPARC-T"

prom_sparc_prefix:

	.asciz	"SPARC-T"

	.asciz	"SPARC-"

	.align	4

prom_root_compatible:

	.skip	64
@@ -396,7 +396,7 @@ sun4v_chip_type: 
	or	%g1, %lo(prom_cpu_compatible), %g1

	sethi	%hi(prom_sparc_prefix), %g7

	or	%g7, %lo(prom_sparc_prefix), %g7

	mov	7, %g3

	mov	6, %g3

90:	ldub	[%g7], %g2

	ldub	[%g1], %g4

	cmp	%g2, %g4
@@ -408,10 +408,23 @@ sun4v_chip_type: 


	sethi	%hi(prom_cpu_compatible), %g1

	or	%g1, %lo(prom_cpu_compatible), %g1

	ldub	[%g1 + 7], %g2

	ldub	[%g1 + 6], %g2

	cmp	%g2, 'T'

	be,pt	%xcc, 70f

	 cmp	%g2, 'M'

	bne,pn	%xcc, 4f

	 nop



70:	ldub	[%g1 + 7], %g2

	cmp	%g2, '3'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA3, %g4

	cmp	%g2, '4'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA4, %g4

	cmp	%g2, '5'

	be,pt	%xcc, 5f

	 mov	SUN4V_CHIP_NIAGARA5, %g4

	ba,pt	%xcc, 4f

	 nop
@@ -543,6 +556,12 @@ niagara_tlb_fixup: 
	be,pt	%xcc, niagara2_patch

	 nop

	cmp	%g1, SUN4V_CHIP_NIAGARA3

	be,pt	%xcc, niagara2_patch

	 nop

	cmp	%g1, SUN4V_CHIP_NIAGARA4

	be,pt	%xcc, niagara2_patch

	 nop

	cmp	%g1, SUN4V_CHIP_NIAGARA5

	be,pt	%xcc, niagara2_patch

	 nop

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