Commit 5fd98eb7 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: dts: uniphier: add MIO DMAC nodes 



Add MIO-DMAC (Media IO DMA Controller) nodes, and use them as
the DMA engine of SD/eMMC controllers.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 072ae88a

arch/arm/boot/dts/uniphier-ld4.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -235,6 +235,16 @@ 
			};

		};



		dmac: dma-controller@5a000000 {

			compatible = "socionext,uniphier-mio-dmac";

			reg = <0x5a000000 0x1000>;

			interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,

				     <0 71 4>, <0 72 4>, <0 73 4>;

			clocks = <&mio_clk 7>;

			resets = <&mio_rst 7>;

			#dma-cells = <1>;

		};



		sd: sdhc@5a400000 {

			compatible = "socionext,uniphier-sd-v2.91";

			status = "disabled";
@@ -246,6 +256,8 @@ 
			clocks = <&mio_clk 0>;

			reset-names = "host", "bridge";

			resets = <&mio_rst 0>, <&mio_rst 3>;

			dma-names = "rx-tx";

			dmas = <&dmac 4>;

			bus-width = <4>;

			cap-sd-highspeed;

			sd-uhs-sdr12;
@@ -263,6 +275,8 @@ 
			clocks = <&mio_clk 1>;

			reset-names = "host", "bridge", "hw";

			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;

			dma-names = "rx-tx";

			dmas = <&dmac 6>;

			bus-width = <8>;

			cap-mmc-highspeed;

			cap-mmc-hw-reset;

arch/arm/boot/dts/uniphier-pro4.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -269,6 +269,16 @@ 
			};

		};



		dmac: dma-controller@5a000000 {

			compatible = "socionext,uniphier-mio-dmac";

			reg = <0x5a000000 0x1000>;

			interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,

				     <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;

			clocks = <&mio_clk 7>;

			resets = <&mio_rst 7>;

			#dma-cells = <1>;

		};



		sd: sdhc@5a400000 {

			compatible = "socionext,uniphier-sd-v2.91";

			status = "disabled";
@@ -280,6 +290,8 @@ 
			clocks = <&mio_clk 0>;

			reset-names = "host", "bridge";

			resets = <&mio_rst 0>, <&mio_rst 3>;

			dma-names = "rx-tx";

			dmas = <&dmac 4>;

			bus-width = <4>;

			cap-sd-highspeed;

			sd-uhs-sdr12;
@@ -297,6 +309,8 @@ 
			clocks = <&mio_clk 1>;

			reset-names = "host", "bridge", "hw";

			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;

			dma-names = "rx-tx";

			dmas = <&dmac 5>;

			bus-width = <8>;

			cap-mmc-highspeed;

			cap-mmc-hw-reset;
@@ -313,6 +327,8 @@ 
			clocks = <&mio_clk 2>;

			reset-names = "host", "bridge";

			resets = <&mio_rst 2>, <&mio_rst 5>;

			dma-names = "rx-tx";

			dmas = <&dmac 6>;

			bus-width = <4>;

			cap-sd-highspeed;

		};

arch/arm/boot/dts/uniphier-sld8.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -239,6 +239,16 @@ 
			};

		};



		dmac: dma-controller@5a000000 {

			compatible = "socionext,uniphier-mio-dmac";

			reg = <0x5a000000 0x1000>;

			interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,

				     <0 71 4>, <0 72 4>, <0 73 4>;

			clocks = <&mio_clk 7>;

			resets = <&mio_rst 7>;

			#dma-cells = <1>;

		};



		sd: sdhc@5a400000 {

			compatible = "socionext,uniphier-sd-v2.91";

			status = "disabled";
@@ -250,6 +260,8 @@ 
			clocks = <&mio_clk 0>;

			reset-names = "host", "bridge";

			resets = <&mio_rst 0>, <&mio_rst 3>;

			dma-names = "rx-tx";

			dmas = <&dmac 4>;

			bus-width = <4>;

			cap-sd-highspeed;

			sd-uhs-sdr12;
@@ -267,6 +279,8 @@ 
			clocks = <&mio_clk 1>;

			reset-names = "host", "bridge", "hw";

			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;

			dma-names = "rx-tx";

			dmas = <&dmac 6>;

			bus-width = <8>;

			cap-mmc-highspeed;

			cap-mmc-hw-reset;

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