Commit 5fa2ec4f authored by Yue Hin Lau's avatar Yue Hin Lau Committed by Alex Deucher
Browse files

drm/amd/display: renaming dpp function to follow naming convention 



Signed-off-by: default avatarYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: default avatarYuehin Lau <Yuehin.Lau@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 37cf55ba

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

+14 −14
Original line number Diff line number Diff line
@@ -442,20 +442,20 @@ static const struct dpp_funcs dcn10_dpp_funcs = { 
		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,

		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,

		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,

		.opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,

		.opp_set_csc_default = dpp1_cm_set_output_csc_default,

		.opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,

		.opp_program_regamma_lut = dpp1_cm_program_regamma_lut,

		.opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,

		.opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,

		.opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,

		.opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,

		.ipp_program_bias_and_scale = dpp1_program_bias_and_scale,

		.ipp_set_degamma = dpp1_set_degamma,

		.ipp_program_input_lut		= dpp1_program_input_lut,

		.ipp_program_degamma_pwl	= dpp1_set_degamma_pwl,

		.ipp_setup			= dpp1_cnv_setup,

		.ipp_full_bypass		= dpp1_full_bypass,

		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,

		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,

		.dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,

		.dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,

		.dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,

		.dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,

		.dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,

		.dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,

		.dpp_program_bias_and_scale = dpp1_program_bias_and_scale,

		.dpp_set_degamma = dpp1_set_degamma,

		.dpp_program_input_lut		= dpp1_program_input_lut,

		.dpp_program_degamma_pwl	= dpp1_set_degamma_pwl,

		.dpp_setup			= dpp1_cnv_setup,

		.dpp_full_bypass		= dpp1_full_bypass,

		.set_cursor_attributes = dpp1_set_cursor_attributes,

		.set_cursor_position = dpp1_set_cursor_position,

};

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+15 −14
Original line number Diff line number Diff line
@@ -869,23 +869,23 @@ static bool dcn10_set_input_transfer_func( 
		tf = plane_state->in_transfer_func;



	if (plane_state->gamma_correction && dce_use_lut(plane_state))

		dpp_base->funcs->ipp_program_input_lut(dpp_base,

		dpp_base->funcs->dpp_program_input_lut(dpp_base,

				plane_state->gamma_correction);



	if (tf == NULL)

		dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);

		dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);

	else if (tf->type == TF_TYPE_PREDEFINED) {

		switch (tf->tf) {

		case TRANSFER_FUNCTION_SRGB:

			dpp_base->funcs->ipp_set_degamma(dpp_base,

			dpp_base->funcs->dpp_set_degamma(dpp_base,

					IPP_DEGAMMA_MODE_HW_sRGB);

			break;

		case TRANSFER_FUNCTION_BT709:

			dpp_base->funcs->ipp_set_degamma(dpp_base,

			dpp_base->funcs->dpp_set_degamma(dpp_base,

					IPP_DEGAMMA_MODE_HW_xvYCC);

			break;

		case TRANSFER_FUNCTION_LINEAR:

			dpp_base->funcs->ipp_set_degamma(dpp_base,

			dpp_base->funcs->dpp_set_degamma(dpp_base,

					IPP_DEGAMMA_MODE_BYPASS);

			break;

		case TRANSFER_FUNCTION_PQ:
@@ -896,7 +896,7 @@ static bool dcn10_set_input_transfer_func( 
			break;

		}

	} else if (tf->type == TF_TYPE_BYPASS) {

		dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);

		dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);

	} else {

		/*TF_TYPE_DISTRIBUTED_POINTS*/

		result = false;
@@ -1235,12 +1235,12 @@ static bool dcn10_set_output_transfer_func( 
			TF_TYPE_PREDEFINED &&

		stream->out_transfer_func->tf ==

			TRANSFER_FUNCTION_SRGB) {

		dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);

		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);

	} else if (dcn10_translate_regamma_to_hw_format(

				stream->out_transfer_func, &dpp->regamma_params)) {

			dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);

			dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);

	} else {

		dpp->funcs->opp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);

		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);

	}



	return true;
@@ -1607,9 +1607,10 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, 


			tbl_entry.color_space = color_space;

			//tbl_entry.regval = matrix;

			pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);



			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);

	} else {

		pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

		pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

	}

}
@@ -1901,7 +1902,7 @@ static void update_dchubp_dpp( 
				);



	// program the input csc

	dpp->funcs->ipp_setup(dpp,

	dpp->funcs->dpp_setup(dpp,

			plane_state->format,

			EXPANSION_MODE_ZERO,

			plane_state->input_csc_color_matrix,
@@ -1909,8 +1910,8 @@ static void update_dchubp_dpp( 


	//set scale and bias registers

	build_prescale_params(&bns_params, plane_state);

	if (dpp->funcs->ipp_program_bias_and_scale)

		dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params);

	if (dpp->funcs->dpp_program_bias_and_scale)

		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);



	mpcc_cfg.dpp_id = hubp->inst;

	mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

+14 −14
Original line number Diff line number Diff line
@@ -62,63 +62,63 @@ struct dpp_funcs { 
			struct dpp *dpp,

			const struct dpp_grph_csc_adjustment *adjust);



	void (*opp_set_csc_default)(

	void (*dpp_set_csc_default)(

		struct dpp *dpp,

		enum dc_color_space colorspace);



	void (*opp_set_csc_adjustment)(

	void (*dpp_set_csc_adjustment)(

		struct dpp *dpp,

		const struct out_csc_color_matrix *tbl_entry);



	void (*opp_power_on_regamma_lut)(

	void (*dpp_power_on_regamma_lut)(

		struct dpp *dpp,

		bool power_on);



	void (*opp_program_regamma_lut)(

	void (*dpp_program_regamma_lut)(

			struct dpp *dpp,

			const struct pwl_result_data *rgb,

			uint32_t num);



	void (*opp_configure_regamma_lut)(

	void (*dpp_configure_regamma_lut)(

			struct dpp *dpp,

			bool is_ram_a);



	void (*opp_program_regamma_lutb_settings)(

	void (*dpp_program_regamma_lutb_settings)(

			struct dpp *dpp,

			const struct pwl_params *params);



	void (*opp_program_regamma_luta_settings)(

	void (*dpp_program_regamma_luta_settings)(

			struct dpp *dpp,

			const struct pwl_params *params);



	void (*opp_program_regamma_pwl)(

	void (*dpp_program_regamma_pwl)(

		struct dpp *dpp,

		const struct pwl_params *params,

		enum opp_regamma mode);



	void (*ipp_program_bias_and_scale)(

	void (*dpp_program_bias_and_scale)(

			struct dpp *dpp,

			struct dc_bias_and_scale *params);



	void (*ipp_set_degamma)(

	void (*dpp_set_degamma)(

			struct dpp *dpp_base,

			enum ipp_degamma_mode mode);



	void (*ipp_program_input_lut)(

	void (*dpp_program_input_lut)(

			struct dpp *dpp_base,

			const struct dc_gamma *gamma);



	void (*ipp_program_degamma_pwl)(struct dpp *dpp_base,

	void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,

									 const struct pwl_params *params);



	void (*ipp_setup)(

	void (*dpp_setup)(

			struct dpp *dpp_base,

			enum surface_pixel_format format,

			enum expansion_mode mode,

			struct csc_transform input_csc_color_matrix,

			enum dc_color_space input_color_space);



	void (*ipp_full_bypass)(struct dpp *dpp_base);

	void (*dpp_full_bypass)(struct dpp *dpp_base);



	void (*set_cursor_attributes)(

			struct dpp *dpp_base,

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