Commit 5f873bae authored by Stephen Warren's avatar Stephen Warren Committed by Greg Kroah-Hartman
Browse files

tty/serial: Fix break handling for PORT_TEGRA 



When a break is received, Tegra's UART apparently fills the FIFO with
0 bytes. These must be drained so that they aren't interpreted as actual
data received. This allows e.g. MAGIC_SYSRQ to work on Tegra's UARTs.

v2: Added FIXME comment to clear_rx_fifo

Originally-by: default avatarLaxman Dewangan <ldewangan@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 4539c24f

drivers/tty/serial/8250.c

+28 −0
Original line number Diff line number Diff line
@@ -1433,6 +1433,27 @@ static void serial8250_enable_ms(struct uart_port *port) 
	serial_out(up, UART_IER, up->ier);

}



/*

 * Clear the Tegra rx fifo after a break

 *

 * FIXME: This needs to become a port specific callback once we have a

 * framework for this

 */

static void clear_rx_fifo(struct uart_8250_port *up)

{

	unsigned int status, tmout = 10000;

	do {

		status = serial_in(up, UART_LSR);

		if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))

			status = serial_in(up, UART_RX);

		else

			break;

		if (--tmout == 0)

			break;

		udelay(1);

	} while (1);

}



static void

receive_chars(struct uart_8250_port *up, unsigned int *status)

{
@@ -1467,6 +1488,13 @@ receive_chars(struct uart_8250_port *up, unsigned int *status) 
			if (lsr & UART_LSR_BI) {

				lsr &= ~(UART_LSR_FE | UART_LSR_PE);

				up->port.icount.brk++;

				/*

				 * If tegra port then clear the rx fifo to

				 * accept another break/character.

				 */

				if (up->port.type == PORT_TEGRA)

					clear_rx_fifo(up);



				/*

				 * We do the SysRQ and SAK checking

				 * here because otherwise the break

include/linux/serial_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ 
#define UART_MCR_DTR		0x01 /* DTR complement */



#define UART_LSR	5	/* In:  Line Status Register */

#define UART_LSR_FIFOE		0x80 /* Fifo error */

#define UART_LSR_TEMT		0x40 /* Transmitter empty */

#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */

#define UART_LSR_BI		0x10 /* Break interrupt indicator */

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