Commit 5f7875d6 authored by Saheed O. Bolarinwa's avatar Saheed O. Bolarinwa Committed by Bjorn Helgaas
Browse files

PCI/ASPM: Remove struct aspm_register_info.latency_encoding 

Previously we stored L0s and L1 Exit Latency information from the Link
Capabilities register in the struct aspm_register_info.

We only need these latencies when we already have the Link Capabilities
values, so use those directly and remove the latencies from struct
aspm_register_info.  No functional change intended.

Link: https://lore.kernel.org/r/20201015193039.12585-7-helgaas@kernel.org


Signed-off-by: default avatarSaheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 67bcc9ad

drivers/pci/pcie/aspm.c

+10 −14
Original line number Diff line number Diff line
@@ -308,8 +308,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) 
}



/* Convert L0s latency encoding to ns */

static u32 calc_l0s_latency(u32 encoding)

static u32 calc_l0s_latency(u32 lnkcap)

{

	u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;



	if (encoding == 0x7)

		return (5 * 1000);	/* > 4us */

	return (64 << encoding);
@@ -324,8 +326,10 @@ static u32 calc_l0s_acceptable(u32 encoding) 
}



/* Convert L1 latency encoding to ns */

static u32 calc_l1_latency(u32 encoding)

static u32 calc_l1_latency(u32 lnkcap)

{

	u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;



	if (encoding == 0x7)

		return (65 * 1000);	/* > 64us */

	return (1000 << encoding);
@@ -381,8 +385,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) 
}



struct aspm_register_info {

	u32 latency_encoding_l0s;

	u32 latency_encoding_l1;

	/* L1 substates */

	u32 l1ss_cap_ptr;

	u32 l1ss_cap;
@@ -393,12 +395,6 @@ struct aspm_register_info { 
static void pcie_get_aspm_reg(struct pci_dev *pdev,

			      struct aspm_register_info *info)

{

	u32 reg32;



	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);

	info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;

	info->latency_encoding_l1  = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;



	/* Read L1 PM substate capabilities */

	info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;

	info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
@@ -594,8 +590,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
		link->aspm_enabled |= ASPM_STATE_L0S_UP;

	if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)

		link->aspm_enabled |= ASPM_STATE_L0S_DW;

	link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);

	link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);

	link->latency_up.l0s = calc_l0s_latency(parent_lnkcap);

	link->latency_dw.l0s = calc_l0s_latency(child_lnkcap);



	/* Setup L1 state */

	if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
@@ -603,8 +599,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 


	if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)

		link->aspm_enabled |= ASPM_STATE_L1;

	link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);

	link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);

	link->latency_up.l1 = calc_l1_latency(parent_lnkcap);

	link->latency_dw.l1 = calc_l1_latency(child_lnkcap);



	/* Setup L1 substate

	 * If we don't have LTR for the entire path from the Root Complex

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