Commit 5f15fbb6 authored by Muralidharan Karicheri's avatar Muralidharan Karicheri Committed by Mauro Carvalho Chehab
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V4L/DVB (12251): v4l: dm644x ccdc module for vpfe capture driver 



This is the hw module for DM644x CCDC. This registers with the
vpfe capture driver and provides a set of hw_ops to configure
CCDC for a specific decoder device connected to the VPFE.

Reviewed by: Hans Verkuil <hverkuil@xs4all.nl>
Reviewed by: Laurent Pinchart <laurent.pinchart@skynet.be>

Signed-off-by: default avatarMuralidharan Karicheri <m-karicheri2@ti.com>
Signed-off-by: default avatarHans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent dd2ceb1a

drivers/media/video/davinci/dm644x_ccdc.c

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File added.

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drivers/media/video/davinci/dm644x_ccdc_regs.h

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/*

 * Copyright (C) 2006-2009 Texas Instruments Inc

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#ifndef _DM644X_CCDC_REGS_H

#define _DM644X_CCDC_REGS_H



/**************************************************************************\

* Register OFFSET Definitions

\**************************************************************************/

#define CCDC_PID				0x0

#define CCDC_PCR				0x4

#define CCDC_SYN_MODE				0x8

#define CCDC_HD_VD_WID				0xc

#define CCDC_PIX_LINES				0x10

#define CCDC_HORZ_INFO				0x14

#define CCDC_VERT_START				0x18

#define CCDC_VERT_LINES				0x1c

#define CCDC_CULLING				0x20

#define CCDC_HSIZE_OFF				0x24

#define CCDC_SDOFST				0x28

#define CCDC_SDR_ADDR				0x2c

#define CCDC_CLAMP				0x30

#define CCDC_DCSUB				0x34

#define CCDC_COLPTN				0x38

#define CCDC_BLKCMP				0x3c

#define CCDC_FPC				0x40

#define CCDC_FPC_ADDR				0x44

#define CCDC_VDINT				0x48

#define CCDC_ALAW				0x4c

#define CCDC_REC656IF				0x50

#define CCDC_CCDCFG				0x54

#define CCDC_FMTCFG				0x58

#define CCDC_FMT_HORZ				0x5c

#define CCDC_FMT_VERT				0x60

#define CCDC_FMT_ADDR0				0x64

#define CCDC_FMT_ADDR1				0x68

#define CCDC_FMT_ADDR2				0x6c

#define CCDC_FMT_ADDR3				0x70

#define CCDC_FMT_ADDR4				0x74

#define CCDC_FMT_ADDR5				0x78

#define CCDC_FMT_ADDR6				0x7c

#define CCDC_FMT_ADDR7				0x80

#define CCDC_PRGEVEN_0				0x84

#define CCDC_PRGEVEN_1				0x88

#define CCDC_PRGODD_0				0x8c

#define CCDC_PRGODD_1				0x90

#define CCDC_VP_OUT				0x94





/***************************************************************

*	Define for various register bit mask and shifts for CCDC

****************************************************************/

#define CCDC_FID_POL_MASK			1

#define CCDC_FID_POL_SHIFT			4

#define CCDC_HD_POL_MASK			1

#define CCDC_HD_POL_SHIFT			3

#define CCDC_VD_POL_MASK			1

#define CCDC_VD_POL_SHIFT			2

#define CCDC_HSIZE_OFF_MASK			0xffffffe0

#define CCDC_32BYTE_ALIGN_VAL			31

#define CCDC_FRM_FMT_MASK			0x1

#define CCDC_FRM_FMT_SHIFT			7

#define CCDC_DATA_SZ_MASK			7

#define CCDC_DATA_SZ_SHIFT			8

#define CCDC_PIX_FMT_MASK			3

#define CCDC_PIX_FMT_SHIFT			12

#define CCDC_VP2SDR_DISABLE			0xFFFBFFFF

#define CCDC_WEN_ENABLE				(1 << 17)

#define CCDC_SDR2RSZ_DISABLE			0xFFF7FFFF

#define CCDC_VDHDEN_ENABLE			(1 << 16)

#define CCDC_LPF_ENABLE				(1 << 14)

#define CCDC_ALAW_ENABLE			(1 << 3)

#define CCDC_ALAW_GAMA_WD_MASK			7

#define CCDC_BLK_CLAMP_ENABLE			(1 << 31)

#define CCDC_BLK_SGAIN_MASK			0x1F

#define CCDC_BLK_ST_PXL_MASK			0x7FFF

#define CCDC_BLK_ST_PXL_SHIFT			10

#define CCDC_BLK_SAMPLE_LN_MASK			7

#define CCDC_BLK_SAMPLE_LN_SHIFT		28

#define CCDC_BLK_SAMPLE_LINE_MASK		7

#define CCDC_BLK_SAMPLE_LINE_SHIFT		25

#define CCDC_BLK_DC_SUB_MASK			0x03FFF

#define CCDC_BLK_COMP_MASK			0xFF

#define CCDC_BLK_COMP_GB_COMP_SHIFT		8

#define CCDC_BLK_COMP_GR_COMP_SHIFT		16

#define CCDC_BLK_COMP_R_COMP_SHIFT		24

#define CCDC_LATCH_ON_VSYNC_DISABLE		(1 << 15)

#define CCDC_FPC_ENABLE				(1 << 15)

#define CCDC_FPC_DISABLE			0

#define CCDC_FPC_FPC_NUM_MASK 			0x7FFF

#define CCDC_DATA_PACK_ENABLE			(1 << 11)

#define CCDC_FMTCFG_VPIN_MASK			7

#define CCDC_FMTCFG_VPIN_SHIFT			12

#define CCDC_FMT_HORZ_FMTLNH_MASK		0x1FFF

#define CCDC_FMT_HORZ_FMTSPH_MASK		0x1FFF

#define CCDC_FMT_HORZ_FMTSPH_SHIFT		16

#define CCDC_FMT_VERT_FMTLNV_MASK		0x1FFF

#define CCDC_FMT_VERT_FMTSLV_MASK		0x1FFF

#define CCDC_FMT_VERT_FMTSLV_SHIFT		16

#define CCDC_VP_OUT_VERT_NUM_MASK		0x3FFF

#define CCDC_VP_OUT_VERT_NUM_SHIFT		17

#define CCDC_VP_OUT_HORZ_NUM_MASK		0x1FFF

#define CCDC_VP_OUT_HORZ_NUM_SHIFT		4

#define CCDC_VP_OUT_HORZ_ST_MASK		0xF

#define CCDC_HORZ_INFO_SPH_SHIFT		16

#define CCDC_VERT_START_SLV0_SHIFT		16

#define CCDC_VDINT_VDINT0_SHIFT			16

#define CCDC_VDINT_VDINT1_MASK			0xFFFF

#define CCDC_PPC_RAW				1

#define CCDC_DCSUB_DEFAULT_VAL			0

#define CCDC_CLAMP_DEFAULT_VAL			0

#define CCDC_ENABLE_VIDEO_PORT			0x8000

#define CCDC_DISABLE_VIDEO_PORT			0

#define CCDC_COLPTN_VAL				0xBB11BB11

#define CCDC_TWO_BYTES_PER_PIXEL		2

#define CCDC_INTERLACED_IMAGE_INVERT		0x4B6D

#define CCDC_INTERLACED_NO_IMAGE_INVERT		0x0249

#define CCDC_PROGRESSIVE_IMAGE_INVERT		0x4000

#define CCDC_PROGRESSIVE_NO_IMAGE_INVERT	0

#define CCDC_INTERLACED_HEIGHT_SHIFT		1

#define CCDC_SYN_MODE_INPMOD_SHIFT		12

#define CCDC_SYN_MODE_INPMOD_MASK		3

#define CCDC_SYN_MODE_8BITS			(7 << 8)

#define CCDC_SYN_FLDMODE_MASK			1

#define CCDC_SYN_FLDMODE_SHIFT			7

#define CCDC_REC656IF_BT656_EN			3

#define CCDC_SYN_MODE_VD_POL_NEGATIVE		(1 << 2)

#define CCDC_CCDCFG_Y8POS_SHIFT			11

#define CCDC_SDOFST_FIELD_INTERLEAVED		0x249

#define CCDC_NO_CULLING				0xffff00ff

#endif

include/media/davinci/dm644x_ccdc.h

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/*

 * Copyright (C) 2006-2009 Texas Instruments Inc

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#ifndef _DM644X_CCDC_H

#define _DM644X_CCDC_H

#include <media/davinci/ccdc_types.h>

#include <media/davinci/vpfe_types.h>



/* enum for No of pixel per line to be avg. in Black Clamping*/

enum ccdc_sample_length {

	CCDC_SAMPLE_1PIXELS,

	CCDC_SAMPLE_2PIXELS,

	CCDC_SAMPLE_4PIXELS,

	CCDC_SAMPLE_8PIXELS,

	CCDC_SAMPLE_16PIXELS

};



/* enum for No of lines in Black Clamping */

enum ccdc_sample_line {

	CCDC_SAMPLE_1LINES,

	CCDC_SAMPLE_2LINES,

	CCDC_SAMPLE_4LINES,

	CCDC_SAMPLE_8LINES,

	CCDC_SAMPLE_16LINES

};



/* enum for Alaw gama width */

enum ccdc_gama_width {

	CCDC_GAMMA_BITS_15_6,

	CCDC_GAMMA_BITS_14_5,

	CCDC_GAMMA_BITS_13_4,

	CCDC_GAMMA_BITS_12_3,

	CCDC_GAMMA_BITS_11_2,

	CCDC_GAMMA_BITS_10_1,

	CCDC_GAMMA_BITS_09_0

};



enum ccdc_data_size {

	CCDC_DATA_16BITS,

	CCDC_DATA_15BITS,

	CCDC_DATA_14BITS,

	CCDC_DATA_13BITS,

	CCDC_DATA_12BITS,

	CCDC_DATA_11BITS,

	CCDC_DATA_10BITS,

	CCDC_DATA_8BITS

};



/* structure for ALaw */

struct ccdc_a_law {

	/* Enable/disable A-Law */

	unsigned char enable;

	/* Gama Width Input */

	enum ccdc_gama_width gama_wd;

};



/* structure for Black Clamping */

struct ccdc_black_clamp {

	unsigned char enable;

	/* only if bClampEnable is TRUE */

	enum ccdc_sample_length sample_pixel;

	/* only if bClampEnable is TRUE */

	enum ccdc_sample_line sample_ln;

	/* only if bClampEnable is TRUE */

	unsigned short start_pixel;

	/* only if bClampEnable is TRUE */

	unsigned short sgain;

	/* only if bClampEnable is FALSE */

	unsigned short dc_sub;

};



/* structure for Black Level Compensation */

struct ccdc_black_compensation {

	/* Constant value to subtract from Red component */

	char r;

	/* Constant value to subtract from Gr component */

	char gr;

	/* Constant value to subtract from Blue component */

	char b;

	/* Constant value to subtract from Gb component */

	char gb;

};



/* structure for fault pixel correction */

struct ccdc_fault_pixel {

	/* Enable or Disable fault pixel correction */

	unsigned char enable;

	/* Number of fault pixel */

	unsigned short fp_num;

	/* Address of fault pixel table */

	unsigned int fpc_table_addr;

};



/* Structure for CCDC configuration parameters for raw capture mode passed

 * by application

 */

struct ccdc_config_params_raw {

	/* data size value from 8 to 16 bits */

	enum ccdc_data_size data_sz;

	/* Structure for Optional A-Law */

	struct ccdc_a_law alaw;

	/* Structure for Optical Black Clamp */

	struct ccdc_black_clamp blk_clamp;

	/* Structure for Black Compensation */

	struct ccdc_black_compensation blk_comp;

	/* Structure for Fault Pixel Module Configuration */

	struct ccdc_fault_pixel fault_pxl;

};





#ifdef __KERNEL__

#include <linux/io.h>

/* Define to enable/disable video port */

#define FP_NUM_BYTES		4

/* Define for extra pixel/line and extra lines/frame */

#define NUM_EXTRAPIXELS		8

#define NUM_EXTRALINES		8



/* settings for commonly used video formats */

#define CCDC_WIN_PAL     {0, 0, 720, 576}

/* ntsc square pixel */

#define CCDC_WIN_VGA	{0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)}



/* Structure for CCDC configuration parameters for raw capture mode */

struct ccdc_params_raw {

	/* pixel format */

	enum ccdc_pixfmt pix_fmt;

	/* progressive or interlaced frame */

	enum ccdc_frmfmt frm_fmt;

	/* video window */

	struct v4l2_rect win;

	/* field id polarity */

	enum vpfe_pin_pol fid_pol;

	/* vertical sync polarity */

	enum vpfe_pin_pol vd_pol;

	/* horizontal sync polarity */

	enum vpfe_pin_pol hd_pol;

	/* interleaved or separated fields */

	enum ccdc_buftype buf_type;

	/*

	 * enable to store the image in inverse

	 * order in memory(bottom to top)

	 */

	unsigned char image_invert_enable;

	/* configurable paramaters */

	struct ccdc_config_params_raw config_params;

};



struct ccdc_params_ycbcr {

	/* pixel format */

	enum ccdc_pixfmt pix_fmt;

	/* progressive or interlaced frame */

	enum ccdc_frmfmt frm_fmt;

	/* video window */

	struct v4l2_rect win;

	/* field id polarity */

	enum vpfe_pin_pol fid_pol;

	/* vertical sync polarity */

	enum vpfe_pin_pol vd_pol;

	/* horizontal sync polarity */

	enum vpfe_pin_pol hd_pol;

	/* enable BT.656 embedded sync mode */

	int bt656_enable;

	/* cb:y:cr:y or y:cb:y:cr in memory */

	enum ccdc_pixorder pix_order;

	/* interleaved or separated fields  */

	enum ccdc_buftype buf_type;

};

#endif

#endif				/* _DM644X_CCDC_H */

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