Commit 5ef28dcc authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'stm32-dt-for-v4.19-1' of... 

Merge tag 'stm32-dt-for-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt

STM32 DT updates for v4.19, round 1

Highlights:
----------

-MCU platforms update:
 -Update RTC syscfg bindings on stm32f746 and stm32f429
 -Update IWDG node with LSI clock name on stm32f429

-MPU STM32MP157 platform update:
 -Add HASH support
 -Add m_can support and enable it on EV1 board
 -Add RTC suppoort and enable it on ED1 board
 -Add USB OTG HS support and enable it on EV1 board
 -Enable USB Host EHCI on EV1 board
 -Add DFSDM support
 -Add SPI support
 -Add ETH support and enable it on EV1 board
 -Add IWDG support and enable it on ED1 board
 -Fix useless GPIO aliases and reorder nodes

* tag 'stm32-dt-for-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32

: (22 commits)
  ARM: dts: stm32: update iwdg with lsi clock name for stm32f429
  ARM: dts: stm32: add iwdg2 support for stm32mp157c-ed1
  ARM: dts: stm32: add iwdg2 support for stm32mp157c
  ARM: dts: stm32: Reorder nodes in stm32mp157c-ed1
  ARM: dts: stm32: remove gpio aliases for stm32mp157c
  ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1
  ARM: dts: stm32: Add ethernet dwmac on stm32mp1
  ARM: dts: stm32: Add syscfg on stm32mp1
  ARM: dts: stm32: add SPI1 support on stm32mp157c-ev1
  ARM: dts: stm32: add SPI support on stm32mp157c
  ARM: dts: stm32: Add DFSDM support to stm32mp157c
  ARM: dts: stm32: Add ADC support to stm32mp157c
  ARM: dts: stm32: enable USB OTG HS on stm32mp157c-ev1
  ARM: dts: stm32: add USB OTG HS support for stm32mp157c SoC
  ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp157c-ev1
  ARM: dts: stm32: enable RTC on stm32mp157c-ed1
  ARM: dts: stm32: add RTC support to stm32mp157c
  ARM: dts: stm32: m_can activation on stm32mp157c-ev1
  ARM: dts: stm32: m_can support to stm32mp157c
  ARM: dts: stm32: Add HASH support on stm32mp157c
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 96a63ce0 c2888cc2

arch/arm/boot/dts/stm32f429.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ 
			interrupt-parent = <&exti>;

			interrupts = <17 1>;

			interrupt-names = "alarm";

			st,syscfg = <&pwrcfg>;

			st,syscfg = <&pwrcfg 0x00 0x100>;

			status = "disabled";

		};
@@ -310,6 +310,7 @@ 
			compatible = "st,stm32-iwdg";

			reg = <0x40003000 0x400>;

			clocks = <&clk_lsi>;

			clock-names = "lsi";

			status = "disabled";

		};

arch/arm/boot/dts/stm32f746.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ 
			interrupt-parent = <&exti>;

			interrupts = <17 1>;

			interrupt-names = "alarm";

			st,syscfg = <&pwrcfg>;

			st,syscfg = <&pwrcfg 0x00 0x100>;

			status = "disabled";

		};

arch/arm/boot/dts/stm32mp157-pinctrl.dtsi

+74 −1
Original line number Diff line number Diff line
@@ -157,6 +157,52 @@ 
				};

			};



			ethernet0_rgmii_pins_a: rgmii-0 {

				pins1 {

					pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */

						 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */

						 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */

						 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */

						 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */

						 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */

						 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */

						 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */

						 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */

					bias-disable;

					drive-push-pull;

					slew-rate = <3>;

				};

				pins2 {

					pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */

						 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */

						 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */

						 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */

						 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */

						 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */

					bias-disable;

				};

			};



			ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {

				pins1 {

					pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */

						 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */

						 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */

						 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */

						 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */

						 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */

						 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */

						 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */

						 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */

						 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */

						 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */

						 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */

						 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */

						 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */

						 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */

				};

			};



			i2c1_pins_a: i2c1-0 {

				pins {

					pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -187,6 +233,19 @@ 
				};

			};



			m_can1_pins_a: m-can1-0 {

				pins1 {

					pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */

					slew-rate = <1>;

					drive-push-pull;

					bias-disable;

				};

				pins2 {

					pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */

					bias-disable;

				};

			};



			pwm2_pins_a: pwm2-0 {

				pins {

					pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@@ -281,7 +340,6 @@ 
			pins-are-numbered;

			interrupt-parent = <&exti>;

			st,syscfg = <&exti 0x60 0xff>;

			status = "disabled";



			gpioz: gpio@54004000 {

				gpio-controller;
@@ -305,6 +363,21 @@ 
					slew-rate = <0>;

				};

			};



			spi1_pins_a: spi1-0 {

				pins1 {

					pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */

						 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */

					bias-disable;

					drive-push-pull;

					slew-rate = <1>;

				};



				pins2 {

					pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */

					bias-disable;

				};

			};

		};

	};

};

arch/arm/boot/dts/stm32mp157c-ed1.dts

+17 −8
Original line number Diff line number Diff line
@@ -49,23 +49,32 @@ 
	};

};



&rng1 {

&i2c4 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c4_pins_a>;

	i2c-scl-rising-time-ns = <185>;

	i2c-scl-falling-time-ns = <20>;

	status = "okay";

};



&timers6 {

&iwdg2 {

	timeout-sec = <32>;

	status = "okay";

	timer@5 {

};



&rng1 {

	status = "okay";

};



&rtc {

	status = "okay";

};



&i2c4 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c4_pins_a>;

	i2c-scl-rising-time-ns = <185>;

	i2c-scl-falling-time-ns = <20>;

&timers6 {

	status = "okay";

	timer@5 {

		status = "okay";

	};

};



&uart4 {

arch/arm/boot/dts/stm32mp157c-ev1.dts

+45 −0
Original line number Diff line number Diff line
@@ -17,6 +17,26 @@ 


	aliases {

		serial0 = &uart4;

		ethernet0 = &ethernet0;

	};

};



&ethernet0 {

	status = "okay";

	pinctrl-0 = <&ethernet0_rgmii_pins_a>;

	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;

	pinctrl-names = "default", "sleep";

	phy-mode = "rgmii";

	max-speed = <1000>;

	phy-handle = <&phy0>;



	mdio0 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "snps,dwmac-mdio";

		phy0: ethernet-phy@0 {

			reg = <0>;

		};

	};

};
@@ -42,6 +62,12 @@ 
	status = "okay";

};



&m_can1 {

	pinctrl-names = "default";

	pinctrl-0 = <&m_can1_pins_a>;

	status = "okay";

};



&qspi {

	pinctrl-names = "default";

	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
@@ -67,6 +93,12 @@ 
	};

};



&spi1 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi1_pins_a>;

	status = "disabled";

};



&timers2 {

	status = "disabled";

	pwm {
@@ -103,6 +135,19 @@ 
	};

};



&usbh_ehci {

	phys = <&usbphyc_port0>;

	phy-names = "usb";

	status = "okay";

};



&usbotg_hs {

	dr_mode = "peripheral";

	phys = <&usbphyc_port1 0>;

	phy-names = "usb2-phy";

	status = "okay";

};



&usbphyc {

	status = "okay";

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE