drm/i915/execlists: Pull the w/a LRI emission into a helper (5ee4a7a6) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_reg.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -156,6 +156,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
		#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
		#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))

		#define __MASKED_FIELD(mask, value) ((mask) << 16 \| (value))
		#define _MASKED_FIELD(mask, value) ({ \
		if (__builtin_constant_p(mask)) \
		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
		@@ -164,7 +165,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
		if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
		BUILD_BUG_ON_MSG((value) & ~(mask), \
		"Incorrect value for mask"); \
		(mask) << 16 \| (value); })
		__MASKED_FIELD(mask, value); })
		#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
		#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))

drivers/gpu/drm/i915/intel_lrc.c

+43 −16

Original line number	Diff line number	Diff line
		@@ -1566,29 +1566,56 @@ static u32 gen8_init_indirectctx_bb(struct intel_engine_cs engine, u32 *batch)
		return batch;
		}

		static u32 gen9_init_indirectctx_bb(struct intel_engine_cs engine, u32 *batch)
		struct lri {
		i915_reg_t reg;
		u32 value;
		};

		static u32 emit_lri(u32 batch, const struct lri *lri, unsigned int count)
		{
		*batch++ = MI_ARB_ON_OFF \| MI_ARB_DISABLE;
		GEM_BUG_ON(!count \|\| count > 63);

		/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
		batch = gen8_emit_flush_coherentl3_wa(engine, batch);
		*batch++ = MI_LOAD_REGISTER_IMM(count);
		do {
		*batch++ = i915_mmio_reg_offset(lri->reg);
		*batch++ = lri->value;
		} while (lri++, --count);
		*batch++ = MI_NOOP;

		*batch++ = MI_LOAD_REGISTER_IMM(3);
		return batch;
		}

		static u32 gen9_init_indirectctx_bb(struct intel_engine_cs engine, u32 *batch)
		{
		static const struct lri lri[] = {
		/* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
		*batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
		*batch++ = _MASKED_BIT_DISABLE(
		GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
		{
		COMMON_SLICE_CHICKEN2,
		__MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
		0),
		},

		/* BSpec: 11391 */
		*batch++ = i915_mmio_reg_offset(FF_SLICE_CHICKEN);
		*batch++ = _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX);
		{
		FF_SLICE_CHICKEN,
		__MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
		FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
		},

		/* BSpec: 11299 */
		*batch++ = i915_mmio_reg_offset(_3D_CHICKEN3);
		*batch++ = _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX);
		{
		_3D_CHICKEN3,
		__MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
		_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
		}
		};

		*batch++ = MI_NOOP;
		*batch++ = MI_ARB_ON_OFF \| MI_ARB_DISABLE;

		/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
		batch = gen8_emit_flush_coherentl3_wa(engine, batch);

		batch = emit_lri(batch, lri, ARRAY_SIZE(lri));

		/* WaClearSlmSpaceAtContextSwitch:kbl */
		/* Actual scratch location is at 128 bytes offset */

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