Commit 5ead67bd authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.10-2020-11-25' of...

Merge tag 'amd-drm-fixes-5.10-2020-11-25' of git://people.freedesktop.org/~agd5f/linux

 into drm-fixes

amd-drm-fixes-5.10-2020-11-25:

amdgpu:
- Runtime pm fix
- SI UVD suspend/resume fix
- HDCP fix for headless cards
- Sienna Cichlid golden register update

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201125151145.4263-1-alexander.deucher@amd.com
parents 030c5b52 60734bd5
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+2 −2
Original line number Diff line number Diff line
@@ -4852,7 +4852,7 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
	if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
		return -ENOTSUPP;

	if (ras && ras->supported)
	if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);

	return amdgpu_dpm_baco_enter(adev);
@@ -4871,7 +4871,7 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
	if (ret)
		return ret;

	if (ras && ras->supported)
	if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);

	return 0;
+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ struct amdgpu_uvd {
	unsigned		harvest_config;
	/* store image width to adjust nb memory state */
	unsigned		decode_image_width;
	uint32_t                keyselect;
};

int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
+2 −0
Original line number Diff line number Diff line
@@ -3105,6 +3105,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] =
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
	SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+11 −9
Original line number Diff line number Diff line
@@ -277,15 +277,8 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
 */
static int uvd_v3_1_fw_validate(struct amdgpu_device *adev)
{
	void *ptr;
	uint32_t ucode_len, i;
	uint32_t keysel;

	ptr = adev->uvd.inst[0].cpu_addr;
	ptr += 192 + 16;
	memcpy(&ucode_len, ptr, 4);
	ptr += ucode_len;
	memcpy(&keysel, ptr, 4);
	int i;
	uint32_t keysel = adev->uvd.keyselect;

	WREG32(mmUVD_FW_START, keysel);

@@ -550,6 +543,8 @@ static int uvd_v3_1_sw_init(void *handle)
	struct amdgpu_ring *ring;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int r;
	void *ptr;
	uint32_t ucode_len;

	/* UVD TRAP */
	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
@@ -571,6 +566,13 @@ static int uvd_v3_1_sw_init(void *handle)
	if (r)
		return r;

	/* Retrieval firmware validate key */
	ptr = adev->uvd.inst[0].cpu_addr;
	ptr += 192 + 16;
	memcpy(&ucode_len, ptr, 4);
	ptr += ucode_len;
	memcpy(&adev->uvd.keyselect, ptr, 4);

	r = amdgpu_uvd_entity_init(adev);

	return r;
+1 −1
Original line number Diff line number Diff line
@@ -1041,7 +1041,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
	amdgpu_dm_init_color_mod();

#ifdef CONFIG_DRM_AMD_DC_HDCP
	if (adev->asic_type >= CHIP_RAVEN) {
	if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
		adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);

		if (!adev->dm.hdcp_workqueue)