Commit 5ea68e02 authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Fix trap state reading for instruction_access_exception. 



1) Read ASI_IMMU SFSR not ASI_DMMU.
2) IMMU has no SFAR, read TPC instead
3) Delete old and incorrect comment about the DTLB protection
   trap having a dependency on the SFSR contents in order to
   function correctly

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bf4e70e5

arch/sparc64/kernel/entry.S

+4 −11
Original line number Diff line number Diff line
@@ -690,11 +690,6 @@ netbsd_syscall: 
	retl

	 nop



	/* These next few routines must be sure to clear the

	 * SFSR FaultValid bit so that the fast tlb data protection

	 * handler does not flush the wrong context and lock up the

	 * box.

	 */

	.globl		__do_data_access_exception

	.globl		__do_data_access_exception_tl1

__do_data_access_exception_tl1:
@@ -733,9 +728,8 @@ __do_instruction_access_exception_tl1: 
	rdpr		%pstate, %g4

	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate

	mov		TLB_SFSR, %g3

	mov		DMMU_SFAR, %g5

	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR

	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR

	ldxa		[%g3] ASI_IMMU, %g4	! Get SFSR

	rdpr		%tpc, %g5		! IMMU has no SFAR, use TPC

	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit

	membar		#Sync

	sethi		%hi(109f), %g7
@@ -752,9 +746,8 @@ __do_instruction_access_exception: 
	rdpr		%pstate, %g4

	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate

	mov		TLB_SFSR, %g3

	mov		DMMU_SFAR, %g5

	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR

	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR

	ldxa		[%g3] ASI_IMMU, %g4	! Get SFSR

	rdpr		%tpc, %g5		! IMMU has no SFAR, use TPC

	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit

	membar		#Sync

	sethi		%hi(109f), %g7

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