Commit 5ea289fe authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Mauro Carvalho Chehab
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[media] s5p-mfc: Rename BANK1/2 to BANK_L/R to better match documentation 



Documentation for MFC hardware still uses 'left' and 'right' names for
the memory channel/banks, so replace BANK1/2 defines with more appropriate
BANK_L/R names.

Suggested-by: default avatarShuah Khan <shuahkhan@gmail.com>
Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent 60641e22

drivers/media/platform/s5p-mfc/s5p_mfc.c

+27 −27
Original line number Diff line number Diff line
@@ -1118,34 +1118,34 @@ static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev) 
	 * Create and initialize virtual devices for accessing

	 * reserved memory regions.

	 */

	mfc_dev->mem_dev[BANK1_CTX] = s5p_mfc_alloc_memdev(dev, "left",

							   BANK1_CTX);

	if (!mfc_dev->mem_dev[BANK1_CTX])

	mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",

							   BANK_L_CTX);

	if (!mfc_dev->mem_dev[BANK_L_CTX])

		return -ENODEV;

	mfc_dev->mem_dev[BANK2_CTX] = s5p_mfc_alloc_memdev(dev, "right",

							   BANK2_CTX);

	if (!mfc_dev->mem_dev[BANK2_CTX]) {

		device_unregister(mfc_dev->mem_dev[BANK1_CTX]);

	mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",

							   BANK_R_CTX);

	if (!mfc_dev->mem_dev[BANK_R_CTX]) {

		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);

		return -ENODEV;

	}



	/* Allocate memory for firmware and initialize both banks addresses */

	ret = s5p_mfc_alloc_firmware(mfc_dev);

	if (ret) {

		device_unregister(mfc_dev->mem_dev[BANK2_CTX]);

		device_unregister(mfc_dev->mem_dev[BANK1_CTX]);

		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);

		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);

		return ret;

	}



	mfc_dev->dma_base[BANK1_CTX] = mfc_dev->fw_buf.dma;

	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;



	bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size,

					&bank2_dma_addr, GFP_KERNEL);

	bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],

				       align_size, &bank2_dma_addr, GFP_KERNEL);

	if (!bank2_virt) {

		mfc_err("Allocating bank2 base failed\n");

		s5p_mfc_release_firmware(mfc_dev);

		device_unregister(mfc_dev->mem_dev[BANK2_CTX]);

		device_unregister(mfc_dev->mem_dev[BANK1_CTX]);

		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);

		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);

		return -ENOMEM;

	}
@@ -1153,14 +1153,14 @@ static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev) 
	 * should not have address of bank2 - MFC will treat it as a null frame.

	 * To avoid such situation we set bank2 address below the pool address.

	 */

	mfc_dev->dma_base[BANK2_CTX] = bank2_dma_addr - align_size;

	mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;



	dma_free_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size, bank2_virt,

	dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,

			  bank2_dma_addr);



	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK1_CTX],

	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],

					DMA_BIT_MASK(32));

	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK2_CTX],

	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],

					DMA_BIT_MASK(32));



	return 0;
@@ -1168,10 +1168,10 @@ static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev) 


static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)

{

	device_unregister(mfc_dev->mem_dev[BANK1_CTX]);

	device_unregister(mfc_dev->mem_dev[BANK2_CTX]);

	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK1_CTX]);

	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK2_CTX]);

	device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);

	device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);

	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);

	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);

}



static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
@@ -1201,8 +1201,8 @@ static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev) 
		return -ENOMEM;

	}

	mfc_dev->mem_size = mem_size;

	mfc_dev->dma_base[BANK1_CTX] = mfc_dev->mem_base;

	mfc_dev->dma_base[BANK2_CTX] = mfc_dev->mem_base;

	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;

	mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;



	/*

	 * MFC hardware cannot handle 0 as a base address, so mark first 128K
@@ -1212,14 +1212,14 @@ static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev) 
		unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;



		bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);

		mfc_dev->dma_base[BANK1_CTX] += offset;

		mfc_dev->dma_base[BANK2_CTX] += offset;

		mfc_dev->dma_base[BANK_L_CTX] += offset;

		mfc_dev->dma_base[BANK_R_CTX] += offset;

	}



	/* Firmware allocation cannot fail in this case */

	s5p_mfc_alloc_firmware(mfc_dev);



	mfc_dev->mem_dev[BANK1_CTX] = mfc_dev->mem_dev[BANK2_CTX] = dev;

	mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;

	vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));



	dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",

drivers/media/platform/s5p-mfc/s5p_mfc_common.h

+2 −2
Original line number Diff line number Diff line
@@ -33,8 +33,8 @@ 
*  while mmaping */

#define DST_QUEUE_OFF_BASE	(1 << 30)



#define BANK1_CTX	0

#define BANK2_CTX	1

#define BANK_L_CTX	0

#define BANK_R_CTX	1

#define BANK_CTX_NUM	2



#define MFC_BANK1_ALIGN_ORDER	13

drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c

+7 −6
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) 
		return -ENOMEM;

	}



	err = s5p_mfc_alloc_priv_buf(dev, BANK1_CTX, &dev->fw_buf);

	err = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->fw_buf);

	if (err) {

		mfc_err("Allocating bitprocessor buffer failed\n");

		return err;
@@ -177,17 +177,18 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev) 
static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)

{

	if (IS_MFCV6_PLUS(dev)) {

		mfc_write(dev, dev->dma_base[BANK1_CTX],

		mfc_write(dev, dev->dma_base[BANK_L_CTX],

			  S5P_FIMV_RISC_BASE_ADDRESS_V6);

		mfc_debug(2, "Base Address : %pad\n",

			  &dev->dma_base[BANK1_CTX]);

			  &dev->dma_base[BANK_L_CTX]);

	} else {

		mfc_write(dev, dev->dma_base[BANK1_CTX],

		mfc_write(dev, dev->dma_base[BANK_L_CTX],

			  S5P_FIMV_MC_DRAMBASE_ADR_A);

		mfc_write(dev, dev->dma_base[BANK2_CTX],

		mfc_write(dev, dev->dma_base[BANK_R_CTX],

			  S5P_FIMV_MC_DRAMBASE_ADR_B);

		mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",

			  &dev->dma_base[BANK1_CTX], &dev->dma_base[BANK2_CTX]);

			  &dev->dma_base[BANK_L_CTX],

			  &dev->dma_base[BANK_R_CTX]);

	}

}

drivers/media/platform/s5p-mfc/s5p_mfc_dec.c

+4 −4
Original line number Diff line number Diff line
@@ -931,14 +931,14 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq, 
		psize[1] = ctx->chroma_size;



		if (IS_MFCV6_PLUS(dev))

			alloc_devs[0] = ctx->dev->mem_dev[BANK1_CTX];

			alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];

		else

			alloc_devs[0] = ctx->dev->mem_dev[BANK2_CTX];

		alloc_devs[1] = ctx->dev->mem_dev[BANK1_CTX];

			alloc_devs[0] = ctx->dev->mem_dev[BANK_R_CTX];

		alloc_devs[1] = ctx->dev->mem_dev[BANK_L_CTX];

	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&

		   ctx->state == MFCINST_INIT) {

		psize[0] = ctx->dec_src_buf_size;

		alloc_devs[0] = ctx->dev->mem_dev[BANK1_CTX];

		alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];

	} else {

		mfc_err("This video node is dedicated to decoding. Decoding not initialized\n");

		return -EINVAL;

drivers/media/platform/s5p-mfc/s5p_mfc_enc.c

+5 −5
Original line number Diff line number Diff line
@@ -1832,7 +1832,7 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq, 
		if (*buf_count > MFC_MAX_BUFFERS)

			*buf_count = MFC_MAX_BUFFERS;

		psize[0] = ctx->enc_dst_buf_size;

		alloc_devs[0] = ctx->dev->mem_dev[BANK1_CTX];

		alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];

	} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {

		if (ctx->src_fmt)

			*plane_count = ctx->src_fmt->num_planes;
@@ -1848,11 +1848,11 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq, 
		psize[1] = ctx->chroma_size;



		if (IS_MFCV6_PLUS(dev)) {

			alloc_devs[0] = ctx->dev->mem_dev[BANK1_CTX];

			alloc_devs[1] = ctx->dev->mem_dev[BANK1_CTX];

			alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];

			alloc_devs[1] = ctx->dev->mem_dev[BANK_L_CTX];

		} else {

			alloc_devs[0] = ctx->dev->mem_dev[BANK2_CTX];

			alloc_devs[1] = ctx->dev->mem_dev[BANK2_CTX];

			alloc_devs[0] = ctx->dev->mem_dev[BANK_R_CTX];

			alloc_devs[1] = ctx->dev->mem_dev[BANK_R_CTX];

		}

	} else {

		mfc_err("invalid queue type: %d\n", vq->type);

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