Commit 5e9eec07 authored by Jonathan Kim's avatar Jonathan Kim Committed by Alex Deucher
Browse files

drm/amdgpu: add perfmons accessible during df c-states 



During DF C-State, Perfmon counters outside of range 1D700-1D7FF will
encounter SLVERR affecting xGMI performance monitoring.  PerfmonCtr[7:4]
is being added to avoid SLVERR during read since it falls within this
range.  PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4].
Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines
will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry
after SLVERR.

Signed-off-by: default avatarJonathan Kim <Jonathan.Kim@amd.com>
Acked-by: default avatarAlex Deucher <Alexander.Deucher@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce73516d

drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h

+16 −0
Original line number Diff line number Diff line
@@ -38,6 +38,14 @@ 
#define smnPerfMonCtlHi2					0x01d464UL

#define smnPerfMonCtlLo3					0x01d470UL

#define smnPerfMonCtlHi3					0x01d474UL

#define smnPerfMonCtlLo4					0x01d880UL

#define smnPerfMonCtlHi4					0x01d884UL

#define smnPerfMonCtlLo5					0x01d888UL

#define smnPerfMonCtlHi5					0x01d88cUL

#define smnPerfMonCtlLo6					0x01d890UL

#define smnPerfMonCtlHi6					0x01d894UL

#define smnPerfMonCtlLo7					0x01d898UL

#define smnPerfMonCtlHi7					0x01d89cUL



#define smnPerfMonCtrLo0					0x01d448UL

#define smnPerfMonCtrHi0					0x01d44cUL
@@ -47,6 +55,14 @@ 
#define smnPerfMonCtrHi2					0x01d46cUL

#define smnPerfMonCtrLo3					0x01d478UL

#define smnPerfMonCtrHi3					0x01d47cUL

#define smnPerfMonCtrLo4					0x01d790UL

#define smnPerfMonCtrHi4					0x01d794UL

#define smnPerfMonCtrLo5					0x01d798UL

#define smnPerfMonCtrHi5					0x01d79cUL

#define smnPerfMonCtrLo6					0x01d7a0UL

#define smnPerfMonCtrHi6					0x01d7a4UL

#define smnPerfMonCtrLo7					0x01d7a8UL

#define smnPerfMonCtrHi7					0x01d7acUL



#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3	0x1d05cUL

#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3		0x1d098UL

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