powerpc/smp: Move powerpc_topology above (5e93f16a) · Commits · 戴 / test

arch/powerpc/kernel/smp.c

+52 −52

Original line number	Diff line number	Diff line
		@@ -819,6 +819,58 @@ out:
		return err;
		}

		static bool shared_caches;

		#ifdef CONFIG_SCHED_SMT
		/* cpumask of CPUs with asymmetric SMT dependency */
		static int powerpc_smt_flags(void)
		{
		int flags = SD_SHARE_CPUCAPACITY \| SD_SHARE_PKG_RESOURCES;

		if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
		printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
		flags \|= SD_ASYM_PACKING;
		}
		return flags;
		}
		#endif

		/*
		* P9 has a slightly odd architecture where pairs of cores share an L2 cache.
		* This topology makes it much cheaper to migrate tasks between adjacent cores
		* since the migrated task remains cache hot. We want to take advantage of this
		* at the scheduler level so an extra topology level is required.
		*/
		static int powerpc_shared_cache_flags(void)
		{
		return SD_SHARE_PKG_RESOURCES;
		}

		/*
		* We can't just pass cpu_l2_cache_mask() directly because
		* returns a non-const pointer and the compiler barfs on that.
		*/
		static const struct cpumask *shared_cache_mask(int cpu)
		{
		return cpu_l2_cache_mask(cpu);
		}

		#ifdef CONFIG_SCHED_SMT
		static const struct cpumask *smallcore_smt_mask(int cpu)
		{
		return cpu_smallcore_mask(cpu);
		}
		#endif

		static struct sched_domain_topology_level powerpc_topology[] = {
		#ifdef CONFIG_SCHED_SMT
		{ cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
		#endif
		{ shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
		{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
		{ NULL, },
		};

		static int init_big_cores(void)
		{
		int cpu;
		@@ -1248,8 +1300,6 @@ static void add_cpu_to_masks(int cpu)
		set_cpus_related(cpu, i, cpu_core_mask);
		}

		static bool shared_caches;

		/* Activate a secondary processor. */
		void start_secondary(void *unused)
		{
		@@ -1313,56 +1363,6 @@ int setup_profiling_timer(unsigned int multiplier)
		return 0;
		}

		#ifdef CONFIG_SCHED_SMT
		/* cpumask of CPUs with asymmetric SMT dependency */
		static int powerpc_smt_flags(void)
		{
		int flags = SD_SHARE_CPUCAPACITY \| SD_SHARE_PKG_RESOURCES;

		if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
		printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
		flags \|= SD_ASYM_PACKING;
		}
		return flags;
		}
		#endif

		/*
		* P9 has a slightly odd architecture where pairs of cores share an L2 cache.
		* This topology makes it much cheaper to migrate tasks between adjacent cores
		* since the migrated task remains cache hot. We want to take advantage of this
		* at the scheduler level so an extra topology level is required.
		*/
		static int powerpc_shared_cache_flags(void)
		{
		return SD_SHARE_PKG_RESOURCES;
		}

		/*
		* We can't just pass cpu_l2_cache_mask() directly because
		* returns a non-const pointer and the compiler barfs on that.
		*/
		static const struct cpumask *shared_cache_mask(int cpu)
		{
		return cpu_l2_cache_mask(cpu);
		}

		#ifdef CONFIG_SCHED_SMT
		static const struct cpumask *smallcore_smt_mask(int cpu)
		{
		return cpu_smallcore_mask(cpu);
		}
		#endif

		static struct sched_domain_topology_level powerpc_topology[] = {
		#ifdef CONFIG_SCHED_SMT
		{ cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
		#endif
		{ shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
		{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
		{ NULL, },
		};

		void __init smp_cpus_done(unsigned int max_cpus)
		{
		/*

Admin message