Commit 5e822e44 authored by Gao Fred's avatar Gao Fred Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Fix guest boot warning 



Simulate MIA core in reset status once GUC engine is reset.

v2: 1. use vgpu_vreg_t() function,
    2. clear MIA_IN_RESET after reading. (Zhenyu)
v3: add comments. (Zhenyu)

Signed-off-by: default avatarGao Fred <fred.gao@intel.com>
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20191216160255.29499-1-fred.gao@intel.com
parent 9f674c81

drivers/gpu/drm/i915/gvt/handlers.c

+16 −0
Original line number Original line Diff line number Diff line
@@ -341,6 +341,10 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
			gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);

			gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);

			engine_mask |= BIT(VCS1);

			engine_mask |= BIT(VCS1);

		}

		}

		if (data & GEN9_GRDOM_GUC) {

			gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);

			vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;

		}

		engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;

		engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;

	}

	}
@@ -1636,6 +1640,16 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 
	return 0;

	return 0;

}

}





static int guc_status_read(struct intel_vgpu *vgpu,

			   unsigned int offset, void *p_data,

			   unsigned int bytes)

{

	/* keep MIA_IN_RESET before clearing */

	read_vreg(vgpu, offset, p_data, bytes);

	vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;

	return 0;

}



static int mmio_read_from_hw(struct intel_vgpu *vgpu,

static int mmio_read_from_hw(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

		unsigned int offset, void *p_data, unsigned int bytes)

{

{
@@ -2672,6 +2686,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 




	MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);

	MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);

	MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);

	MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);

	MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);



	return 0;

	return 0;

}

}

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