Commit 5e66403e authored Jan 16, 2020 by Dennis Li Committed by Alex Deucher Jan 22, 2020

drm/amdgpu: refine the security check for RAS functions



To avoid calling RAS related functions when RAS feature isn't
supported in hardware. Change to check supported features, instead
of checking asic type.

v2: reuse amdgpu_ras_is_supported function, instead of introducing
a new flag for hardware ras feature.

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 39aa0ef1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -5994,7 +5994,7 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
		int ret;
		struct ta_ras_trigger_error_input block_info = { 0 };

		if (adev->asic_type != CHIP_VEGA20)
		if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
		return -EINVAL;

		if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks))
		@@ -6245,7 +6245,7 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
		uint32_t i, j, k;
		uint32_t reg_value;

		if (adev->asic_type != CHIP_VEGA20)
		if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
		return -EINVAL;

		err_data->ue_count = 0;

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