Commit 5e3b4a15 authored Dec 20, 2017 by Sohil Mehta Committed by Joerg Roedel Jan 17, 2018

iommu/vt-d: Enable upto 57 bits of domain address width



Update the IOMMU default domain address width to 57 bits. This would
enable the IOMMU to do upto 5-levels of paging for second level
translations - IOVA translation requests without PASID.

Even though the maximum supported address width is being increased to
57, __iommu_calculate_agaw() would set the actual supported address
width to the maximum support available in IOMMU hardware.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent 9d2e6505

drivers/iommu/intel-iommu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -64,7 +64,7 @@
		#define IOAPIC_RANGE_END (0xfeefffff)
		#define IOVA_START_ADDR (0x1000)

		#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
		#define DEFAULT_DOMAIN_ADDRESS_WIDTH 57

		#define MAX_AGAW_WIDTH 64
		#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)

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