Commit 5e335add authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: early return when pipe_cnt is 0 in bw validation



[Why]
Unintentionally introduced behaviour change from previous refactor,
which causes clks to be 0 in no stream cases, which will cause
divide by 0.

[How]
Skip calculation of clocks when no stream. Which is the same as old
behaviour.

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Reviewed-by: default avatarTony Cheng <tong.cheng@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64af142a
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+7 −1
Original line number Diff line number Diff line
@@ -2022,6 +2022,7 @@ bool dcn20_fast_validate_bw(
		struct dc *dc,
		struct dc_state *context,
		display_e2e_pipe_params_st *pipes,
		int *pipe_cnt_out,
		int *pipe_split_from,
		int *vlevel_out)
{
@@ -2074,6 +2075,8 @@ bool dcn20_fast_validate_bw(
		pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
			&context->res_ctx, pipes);

	*pipe_cnt_out = pipe_cnt;

	if (!pipe_cnt) {
		out = true;
		goto validate_out;
@@ -2434,7 +2437,10 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

	BW_VAL_TRACE_COUNT();

	out = dcn20_fast_validate_bw(dc, context, pipes, pipe_split_from, &vlevel);
	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);

	if (pipe_cnt == 0)
		goto validate_out;

	if (!out)
		goto validate_fail;
+1 −0
Original line number Diff line number Diff line
@@ -120,6 +120,7 @@ bool dcn20_fast_validate_bw(
		struct dc *dc,
		struct dc_state *context,
		display_e2e_pipe_params_st *pipes,
		int *pipe_cnt_out,
		int *pipe_split_from,
		int *vlevel_out);
void dcn20_calculate_dlg_params(