Commit 5df83111 authored by Qipan Li's avatar Qipan Li Committed by Greg Kroah-Hartman
Browse files

serial: sirf: make the driver also support USP-based UART 



Universal Serial Ports (USP) can be used as PCM, UART, SPI,
I2S etc. this makes the USP work as UART. the basic work
flow is same with UART controller, the main difference will
be offset of registers and bits.

this patch makes the old sirfsoc uart driver support both
sirf UART and USP-based UART by making their differences
become private data.

Signed-off-by: default avatarQipan Li <Qipan.Li@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 909102db

drivers/tty/serial/sirfsoc_uart.c

+346 −194

File changed.

Preview size limit exceeded, changes collapsed.

drivers/tty/serial/sirfsoc_uart.h

+309 −104
Original line number Diff line number Diff line
@@ -6,32 +6,260 @@ 
 * Licensed under GPLv2 or later.

 */

#include <linux/bitops.h>

struct sirfsoc_uart_param {

	const char *uart_name;

	const char *port_name;

	u32 uart_nr;

	u32 register_uart_nr;

};



/* UART Register Offset Define */

#define SIRFUART_LINE_CTRL			0x0040

#define SIRFUART_TX_RX_EN			0x004c

#define SIRFUART_DIVISOR			0x0050

#define SIRFUART_INT_EN				0x0054

#define SIRFUART_INT_STATUS			0x0058

#define SIRFUART_INT_EN_CLR			0x0060

#define SIRFUART_TX_DMA_IO_CTRL			0x0100

#define SIRFUART_TX_DMA_IO_LEN			0x0104

#define SIRFUART_TX_FIFO_CTRL			0x0108

#define SIRFUART_TX_FIFO_LEVEL_CHK		0x010C

#define SIRFUART_TX_FIFO_OP			0x0110

#define SIRFUART_TX_FIFO_STATUS			0x0114

#define SIRFUART_TX_FIFO_DATA			0x0118

#define SIRFUART_RX_DMA_IO_CTRL			0x0120

#define SIRFUART_RX_DMA_IO_LEN			0x0124

#define SIRFUART_RX_FIFO_CTRL			0x0128

#define SIRFUART_RX_FIFO_LEVEL_CHK		0x012C

#define SIRFUART_RX_FIFO_OP			0x0130

#define SIRFUART_RX_FIFO_STATUS			0x0134

#define SIRFUART_RX_FIFO_DATA			0x0138

#define SIRFUART_AFC_CTRL			0x0140

#define SIRFUART_SWH_DMA_IO			0x0148



/* UART Line Control Register */

struct sirfsoc_register {

	/* hardware uart specific */

	u32 sirfsoc_line_ctrl;

	u32 sirfsoc_divisor;

	/* uart - usp common */

	u32 sirfsoc_tx_rx_en;

	u32 sirfsoc_int_en_reg;

	u32 sirfsoc_int_st_reg;

	u32 sirfsoc_tx_dma_io_ctrl;

	u32 sirfsoc_tx_dma_io_len;

	u32 sirfsoc_tx_fifo_ctrl;

	u32 sirfsoc_tx_fifo_level_chk;

	u32 sirfsoc_tx_fifo_op;

	u32 sirfsoc_tx_fifo_status;

	u32 sirfsoc_tx_fifo_data;

	u32 sirfsoc_rx_dma_io_ctrl;

	u32 sirfsoc_rx_dma_io_len;

	u32 sirfsoc_rx_fifo_ctrl;

	u32 sirfsoc_rx_fifo_level_chk;

	u32 sirfsoc_rx_fifo_op;

	u32 sirfsoc_rx_fifo_status;

	u32 sirfsoc_rx_fifo_data;

	u32 sirfsoc_afc_ctrl;

	u32 sirfsoc_swh_dma_io;

	/* hardware usp specific */

	u32 sirfsoc_mode1;

	u32 sirfsoc_mode2;

	u32 sirfsoc_tx_frame_ctrl;

	u32 sirfsoc_rx_frame_ctrl;

	u32 sirfsoc_async_param_reg;

};



typedef u32 (*fifo_full_mask)(int line);

typedef u32 (*fifo_empty_mask)(int line);



struct sirfsoc_fifo_status {

	fifo_full_mask ff_full;

	fifo_empty_mask ff_empty;

};



struct sirfsoc_int_en {

	u32 sirfsoc_rx_done_en;

	u32 sirfsoc_tx_done_en;

	u32 sirfsoc_rx_oflow_en;

	u32 sirfsoc_tx_allout_en;

	u32 sirfsoc_rx_io_dma_en;

	u32 sirfsoc_tx_io_dma_en;

	u32 sirfsoc_rxfifo_full_en;

	u32 sirfsoc_txfifo_empty_en;

	u32 sirfsoc_rxfifo_thd_en;

	u32 sirfsoc_txfifo_thd_en;

	u32 sirfsoc_frm_err_en;

	u32 sirfsoc_rxd_brk_en;

	u32 sirfsoc_rx_timeout_en;

	u32 sirfsoc_parity_err_en;

	u32 sirfsoc_cts_en;

	u32 sirfsoc_rts_en;

};



struct sirfsoc_int_status {

	u32 sirfsoc_rx_done;

	u32 sirfsoc_tx_done;

	u32 sirfsoc_rx_oflow;

	u32 sirfsoc_tx_allout;

	u32 sirfsoc_rx_io_dma;

	u32 sirfsoc_tx_io_dma;

	u32 sirfsoc_rxfifo_full;

	u32 sirfsoc_txfifo_empty;

	u32 sirfsoc_rxfifo_thd;

	u32 sirfsoc_txfifo_thd;

	u32 sirfsoc_frm_err;

	u32 sirfsoc_rxd_brk;

	u32 sirfsoc_rx_timeout;

	u32 sirfsoc_parity_err;

	u32 sirfsoc_cts;

	u32 sirfsoc_rts;

};



enum sirfsoc_uart_type {

	SIRF_REAL_UART,

	SIRF_USP_UART,

};



struct sirfsoc_uart_register {

	struct sirfsoc_register uart_reg;

	struct sirfsoc_int_en uart_int_en;

	struct sirfsoc_int_status uart_int_st;

	struct sirfsoc_fifo_status fifo_status;

	struct sirfsoc_uart_param uart_param;

	enum sirfsoc_uart_type uart_type;

};



u32 usp_ff_full(int line)

{

	return 0x80;

}

u32 usp_ff_empty(int line)

{

	return 0x100;

}

u32 uart_ff_full(int line)

{

	return (line == 1) ? (0x20) : (0x80);

}

u32 uart_ff_empty(int line)

{

	return (line == 1) ? (0x40) : (0x100);

}

struct sirfsoc_uart_register sirfsoc_usp = {

	.uart_reg = {

		.sirfsoc_mode1		= 0x0000,

		.sirfsoc_mode2		= 0x0004,

		.sirfsoc_tx_frame_ctrl	= 0x0008,

		.sirfsoc_rx_frame_ctrl	= 0x000c,

		.sirfsoc_tx_rx_en	= 0x0010,

		.sirfsoc_int_en_reg	= 0x0014,

		.sirfsoc_int_st_reg	= 0x0018,

		.sirfsoc_async_param_reg = 0x0024,

		.sirfsoc_tx_dma_io_ctrl	= 0x0100,

		.sirfsoc_tx_dma_io_len	= 0x0104,

		.sirfsoc_tx_fifo_ctrl	= 0x0108,

		.sirfsoc_tx_fifo_level_chk = 0x010c,

		.sirfsoc_tx_fifo_op	= 0x0110,

		.sirfsoc_tx_fifo_status	= 0x0114,

		.sirfsoc_tx_fifo_data	= 0x0118,

		.sirfsoc_rx_dma_io_ctrl	= 0x0120,

		.sirfsoc_rx_dma_io_len	= 0x0124,

		.sirfsoc_rx_fifo_ctrl	= 0x0128,

		.sirfsoc_rx_fifo_level_chk = 0x012c,

		.sirfsoc_rx_fifo_op	= 0x0130,

		.sirfsoc_rx_fifo_status	= 0x0134,

		.sirfsoc_rx_fifo_data	= 0x0138,

	},

	.uart_int_en = {

		.sirfsoc_rx_done_en	= BIT(0),

		.sirfsoc_tx_done_en	= BIT(1),

		.sirfsoc_rx_oflow_en	= BIT(2),

		.sirfsoc_tx_allout_en	= BIT(3),

		.sirfsoc_rx_io_dma_en	= BIT(4),

		.sirfsoc_tx_io_dma_en	= BIT(5),

		.sirfsoc_rxfifo_full_en	= BIT(6),

		.sirfsoc_txfifo_empty_en = BIT(7),

		.sirfsoc_rxfifo_thd_en	= BIT(8),

		.sirfsoc_txfifo_thd_en	= BIT(9),

		.sirfsoc_frm_err_en	= BIT(10),

		.sirfsoc_rx_timeout_en	= BIT(11),

		.sirfsoc_rxd_brk_en	= BIT(15),

	},

	.uart_int_st = {

		.sirfsoc_rx_done	= BIT(0),

		.sirfsoc_tx_done	= BIT(1),

		.sirfsoc_rx_oflow	= BIT(2),

		.sirfsoc_tx_allout	= BIT(3),

		.sirfsoc_rx_io_dma	= BIT(4),

		.sirfsoc_tx_io_dma	= BIT(5),

		.sirfsoc_rxfifo_full	= BIT(6),

		.sirfsoc_txfifo_empty	= BIT(7),

		.sirfsoc_rxfifo_thd	= BIT(8),

		.sirfsoc_txfifo_thd	= BIT(9),

		.sirfsoc_frm_err	= BIT(10),

		.sirfsoc_rx_timeout	= BIT(11),

		.sirfsoc_rxd_brk	= BIT(15),

	},

	.fifo_status = {

		.ff_full		= usp_ff_full,

		.ff_empty		= usp_ff_empty,

	},

	.uart_param = {

		.uart_name = "ttySiRF",

		.port_name = "sirfsoc-uart",

		.uart_nr = 2,

		.register_uart_nr = 3,

	},

};



struct sirfsoc_uart_register sirfsoc_uart = {

	.uart_reg = {

		.sirfsoc_line_ctrl	= 0x0040,

		.sirfsoc_tx_rx_en	= 0x004c,

		.sirfsoc_divisor	= 0x0050,

		.sirfsoc_int_en_reg	= 0x0054,

		.sirfsoc_int_st_reg	= 0x0058,

		.sirfsoc_tx_dma_io_ctrl	= 0x0100,

		.sirfsoc_tx_dma_io_len	= 0x0104,

		.sirfsoc_tx_fifo_ctrl	= 0x0108,

		.sirfsoc_tx_fifo_level_chk = 0x010c,

		.sirfsoc_tx_fifo_op	= 0x0110,

		.sirfsoc_tx_fifo_status	= 0x0114,

		.sirfsoc_tx_fifo_data	= 0x0118,

		.sirfsoc_rx_dma_io_ctrl	= 0x0120,

		.sirfsoc_rx_dma_io_len	= 0x0124,

		.sirfsoc_rx_fifo_ctrl	= 0x0128,

		.sirfsoc_rx_fifo_level_chk = 0x012c,

		.sirfsoc_rx_fifo_op	= 0x0130,

		.sirfsoc_rx_fifo_status	= 0x0134,

		.sirfsoc_rx_fifo_data	= 0x0138,

		.sirfsoc_afc_ctrl	= 0x0140,

		.sirfsoc_swh_dma_io	= 0x0148,

	},

	.uart_int_en = {

		.sirfsoc_rx_done_en	= BIT(0),

		.sirfsoc_tx_done_en	= BIT(1),

		.sirfsoc_rx_oflow_en	= BIT(2),

		.sirfsoc_tx_allout_en	= BIT(3),

		.sirfsoc_rx_io_dma_en	= BIT(4),

		.sirfsoc_tx_io_dma_en	= BIT(5),

		.sirfsoc_rxfifo_full_en	= BIT(6),

		.sirfsoc_txfifo_empty_en = BIT(7),

		.sirfsoc_rxfifo_thd_en	= BIT(8),

		.sirfsoc_txfifo_thd_en	= BIT(9),

		.sirfsoc_frm_err_en	= BIT(10),

		.sirfsoc_rxd_brk_en	= BIT(11),

		.sirfsoc_rx_timeout_en	= BIT(12),

		.sirfsoc_parity_err_en	= BIT(13),

		.sirfsoc_cts_en		= BIT(14),

		.sirfsoc_rts_en		= BIT(15),

	},

	.uart_int_st = {

		.sirfsoc_rx_done	= BIT(0),

		.sirfsoc_tx_done	= BIT(1),

		.sirfsoc_rx_oflow	= BIT(2),

		.sirfsoc_tx_allout	= BIT(3),

		.sirfsoc_rx_io_dma	= BIT(4),

		.sirfsoc_tx_io_dma	= BIT(5),

		.sirfsoc_rxfifo_full	= BIT(6),

		.sirfsoc_txfifo_empty	= BIT(7),

		.sirfsoc_rxfifo_thd	= BIT(8),

		.sirfsoc_txfifo_thd	= BIT(9),

		.sirfsoc_frm_err	= BIT(10),

		.sirfsoc_rxd_brk	= BIT(11),

		.sirfsoc_rx_timeout	= BIT(12),

		.sirfsoc_parity_err	= BIT(13),

		.sirfsoc_cts		= BIT(14),

		.sirfsoc_rts		= BIT(15),

	},

	.fifo_status = {

		.ff_full		= uart_ff_full,

		.ff_empty		= uart_ff_empty,

	},

	.uart_param = {

		.uart_name = "ttySiRF",

		.port_name = "sirfsoc_uart",

		.uart_nr = 3,

		.register_uart_nr = 0,

	},

};

/* uart io ctrl */

#define SIRFUART_DATA_BIT_LEN_MASK		0x3

#define SIRFUART_DATA_BIT_LEN_5			BIT(0)

#define SIRFUART_DATA_BIT_LEN_6			1
@@ -51,89 +279,65 @@ 
#define SIRFUART_LOOP_BACK			BIT(7)

#define SIRFUART_PARITY_MASK			(7 << 3)

#define SIRFUART_DUMMY_READ			BIT(16)



#define SIRFSOC_UART_RX_TIMEOUT(br, to)	(((br) * (((to) + 999) / 1000)) / 1000)

#define SIRFUART_RECV_TIMEOUT_MASK	(0xFFFF << 16)

#define SIRFUART_RECV_TIMEOUT(x)	(((x) & 0xFFFF) << 16)



/* UART Auto Flow Control */

#define SIRFUART_AFC_RX_THD_MASK		0x000000FF

#define SIRFUART_AFC_CTRL_RX_THD		0x70

#define SIRFUART_AFC_RX_EN			BIT(8)

#define SIRFUART_AFC_TX_EN			BIT(9)

#define SIRFUART_CTS_CTRL			BIT(10)

#define SIRFUART_RTS_CTRL			BIT(11)

#define SIRFUART_CTS_IN_STATUS			BIT(12)

#define SIRFUART_RTS_OUT_STATUS			BIT(13)



/* UART Interrupt Enable Register */

#define SIRFUART_RX_DONE_INT			BIT(0)

#define SIRFUART_TX_DONE_INT			BIT(1)

#define SIRFUART_RX_OFLOW_INT			BIT(2)

#define SIRFUART_TX_ALLOUT_INT			BIT(3)

#define SIRFUART_RX_IO_DMA_INT			BIT(4)

#define SIRFUART_TX_IO_DMA_INT			BIT(5)

#define SIRFUART_RXFIFO_FULL_INT		BIT(6)

#define SIRFUART_TXFIFO_EMPTY_INT		BIT(7)

#define SIRFUART_RXFIFO_THD_INT			BIT(8)

#define SIRFUART_TXFIFO_THD_INT			BIT(9)

#define SIRFUART_FRM_ERR_INT			BIT(10)

#define SIRFUART_RXD_BREAK_INT			BIT(11)

#define SIRFUART_RX_TIMEOUT_INT			BIT(12)

#define SIRFUART_PARITY_ERR_INT			BIT(13)

#define SIRFUART_CTS_INT_EN			BIT(14)

#define SIRFUART_RTS_INT_EN			BIT(15)



/* UART Interrupt Status Register */

#define SIRFUART_RX_DONE			BIT(0)

#define SIRFUART_TX_DONE			BIT(1)

#define SIRFUART_RX_OFLOW			BIT(2)

#define SIRFUART_TX_ALL_EMPTY			BIT(3)

#define SIRFUART_DMA_IO_RX_DONE			BIT(4)

#define SIRFUART_DMA_IO_TX_DONE			BIT(5)

#define SIRFUART_RXFIFO_FULL			BIT(6)

#define SIRFUART_TXFIFO_EMPTY			BIT(7)

#define SIRFUART_RXFIFO_THD_REACH		BIT(8)

#define SIRFUART_TXFIFO_THD_REACH		BIT(9)

#define SIRFUART_FRM_ERR			BIT(10)

#define SIRFUART_RXD_BREAK			BIT(11)

#define SIRFUART_RX_TIMEOUT			BIT(12)

#define SIRFUART_PARITY_ERR			BIT(13)

#define SIRFUART_CTS_CHANGE			BIT(14)

#define SIRFUART_RTS_CHANGE			BIT(15)

#define SIRFUART_PLUG_IN			BIT(16)



#define SIRFUART_ERR_INT_STAT					\

				(SIRFUART_RX_OFLOW |		\

				SIRFUART_FRM_ERR |		\

				SIRFUART_RXD_BREAK |		\

				SIRFUART_PARITY_ERR)

#define SIRFUART_ERR_INT_EN					\

				(SIRFUART_RX_OFLOW_INT |	\

				SIRFUART_FRM_ERR_INT |		\

				SIRFUART_RXD_BREAK_INT |	\

				SIRFUART_PARITY_ERR_INT)

#define SIRFUART_TX_INT_EN	SIRFUART_TXFIFO_EMPTY_INT

#define SIRFUART_RX_IO_INT_EN					\

				(SIRFUART_RX_TIMEOUT_INT |	\

				SIRFUART_RXFIFO_THD_INT |	\

				SIRFUART_RXFIFO_FULL_INT |	\

				SIRFUART_ERR_INT_EN)



#define SIRFUART_AFC_CTS_CTRL			BIT(10)

#define SIRFUART_AFC_RTS_CTRL			BIT(11)

#define	SIRFUART_AFC_CTS_STATUS			BIT(12)

#define	SIRFUART_AFC_RTS_STATUS			BIT(13)

/* UART FIFO Register */

#define SIRFUART_TX_FIFO_STOP			0x0

#define SIRFUART_TX_FIFO_RESET			0x1

#define SIRFUART_TX_FIFO_START			0x2

#define SIRFUART_RX_FIFO_STOP			0x0

#define SIRFUART_RX_FIFO_RESET			0x1

#define SIRFUART_RX_FIFO_START			0x2

#define SIRFUART_TX_MODE_DMA			0

#define SIRFUART_TX_MODE_IO			1

#define SIRFUART_RX_MODE_DMA			0

#define SIRFUART_RX_MODE_IO			1



#define SIRFUART_RX_EN				0x1

#define SIRFUART_TX_EN				0x2

#define SIRFUART_FIFO_STOP			0x0

#define SIRFUART_FIFO_RESET			BIT(0)

#define SIRFUART_FIFO_START			BIT(1)



#define SIRFUART_RX_EN				BIT(0)

#define SIRFUART_TX_EN				BIT(1)



#define SIRFUART_IO_MODE			BIT(0)

#define SIRFUART_DMA_MODE			0x0



/* Macro Specific*/

#define SIRFUART_INT_EN_CLR                    0x0060

/* Baud Rate Calculation */

#define SIRF_MIN_SAMPLE_DIV			0xf

#define SIRF_MAX_SAMPLE_DIV			0x3f

#define SIRF_IOCLK_DIV_MAX			0xffff

#define SIRF_SAMPLE_DIV_SHIFT			16

#define SIRF_IOCLK_DIV_MASK			0xffff

#define SIRF_SAMPLE_DIV_MASK			0x3f0000

#define SIRF_BAUD_RATE_SUPPORT_NR		18



/* USP SPEC */

#define SIRFSOC_USP_ENDIAN_CTRL_LSBF		BIT(4)

#define SIRFSOC_USP_EN				BIT(5)



/* USP-UART Common */

#define SIRFSOC_UART_RX_TIMEOUT(br, to)	(((br) * (((to) + 999) / 1000)) / 1000)

#define SIRFUART_RECV_TIMEOUT_VALUE(x)	\

				(((x) > 0xFFFF) ? 0xFFFF : ((x) & 0xFFFF))

#define SIRFUART_RECV_TIMEOUT(port, x)	\

		(((port)->line > 2) ? (x & 0xFFFF) : ((x) & 0xFFFF) << 16)



#define SIRFUART_FIFO_THD(port)		((port->line) == 1 ? 16 : 64)

#define SIRFUART_ERR_INT_STAT(port, unit_st)			\

				(uint_st->sirfsoc_rx_oflow |		\

				uint_st->sirfsoc_frm_err |		\

				uint_st->sirfsoc_rxd_brk |		\

		((port->line > 2) ? 0 : uint_st->sirfsoc_parity_err))

#define SIRFUART_RX_IO_INT_EN(port, uint_en)				\

				(uint_en->sirfsoc_rx_timeout_en |\

				 uint_en->sirfsoc_rxfifo_thd_en |\

				 uint_en->sirfsoc_rxfifo_full_en |\

				 uint_en->sirfsoc_frm_err_en |\

				 uint_en->sirfsoc_rx_oflow_en |\

				 uint_en->sirfsoc_rxd_brk_en |\

		((port->line > 2) ? 0 : uint_en->sirfsoc_parity_err_en))

#define SIRFUART_RX_IO_INT_ST(uint_st)				\

				(uint_st->sirfsoc_rx_timeout |\

				 uint_st->sirfsoc_rxfifo_thd |\

				 uint_st->sirfsoc_rxfifo_full)

#define SIRFUART_CTS_INT_ST(uint_st)	(uint_st->sirfsoc_cts)

/* Generic Definitions */

#define SIRFSOC_UART_NAME			"ttySiRF"

#define SIRFSOC_UART_MAJOR			0
@@ -167,6 +371,7 @@ struct sirfsoc_uart_port { 
	struct clk			*clk;

	/* for SiRFmarco, there are SET/CLR for UART_INT_EN */

	bool				is_marco;

	struct sirfsoc_uart_register	*uart_reg;

};



/* Hardware Flow Control */

CRA Git | Maintained and supported by SUSTech CRA and CCSE