ARM: OMAP2+: clock: Remove all direct dereferencing of struct clk (5dcc3b97) · Commits · 戴 / test

arch/arm/mach-omap2/clkt2xxx_apll.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
		omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

		omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
		OMAP24XX_CM_IDLEST_VAL, clk->name);
		OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));

		/*
		* REVISIT: Should we return an error code if omap2_wait_clock_ready()

arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c

+7 −3

Original line number	Diff line number	Diff line
		@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
		long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
		{
		const struct prcm_config *ptr;
		long highest_rate;
		long highest_rate, sys_clk_rate;

		highest_rate = -EINVAL;
		sys_clk_rate = __clk_get_rate(sclk);

		for (ptr = rate_table; ptr->mpu_speed; ptr++) {
		if (!(ptr->flags & cpu_mask))
		continue;
		if (ptr->xtal_speed != sclk->rate)
		if (ptr->xtal_speed != sys_clk_rate)
		continue;

		highest_rate = ptr->mpu_speed;
		@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
		const struct prcm_config *prcm;
		unsigned long found_speed = 0;
		unsigned long flags;
		long sys_clk_rate;

		sys_clk_rate = __clk_get_rate(sclk);

		for (prcm = rate_table; prcm->mpu_speed; prcm++) {
		if (!(prcm->flags & cpu_mask))
		continue;

		if (prcm->xtal_speed != sclk->rate)
		if (prcm->xtal_speed != sys_clk_rate)
		continue;

		if (prcm->mpu_speed <= rate) {

arch/arm/mach-omap2/clkt34xx_dpll3m2.c

+11 −9

Original line number	Diff line number	Diff line
		@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
		struct omap_sdrc_params *sdrc_cs0;
		struct omap_sdrc_params *sdrc_cs1;
		int ret;
		unsigned long clkrate;

		if (!clk \|\| !rate)
		return -EINVAL;
		@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
		if (validrate != rate)
		return -EINVAL;

		sdrcrate = sdrc_ick_p->rate;
		if (rate > clk->rate)
		sdrcrate <<= ((rate / clk->rate) >> 1);
		sdrcrate = __clk_get_rate(sdrc_ick_p);
		clkrate = __clk_get_rate(clk);
		if (rate > clkrate)
		sdrcrate <<= ((rate / clkrate) >> 1);
		else
		sdrcrate >>= ((clk->rate / rate) >> 1);
		sdrcrate >>= ((clkrate / rate) >> 1);

		ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
		if (ret)
		@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
		/*
		* XXX This only needs to be done when the CPU frequency changes
		*/
		_mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
		_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
		c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
		c += 1; /* for safety */
		c *= SDRC_MPURATE_LOOPS;
		@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
		if (c == 0)
		c = 1;

		pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
		validrate);
		pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
		clkrate, validrate);
		pr_debug("clock: SDRC CS0 timing params used:"
		" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
		sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
		@@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)

		if (sdrc_cs1)
		omap3_configure_core_dpll(
		new_div, unlock_dll, c, rate > clk->rate,
		new_div, unlock_dll, c, rate > clkrate,
		sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
		sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
		sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
		sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
		else
		omap3_configure_core_dpll(
		new_div, unlock_dll, c, rate > clk->rate,
		new_div, unlock_dll, c, rate > clkrate,
		sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
		sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
		0, 0, 0, 0);

arch/arm/mach-omap2/clkt_clksel.c

+57 −34

Original line number	Diff line number	Diff line
		@@ -71,8 +71,8 @@ static const struct clksel _get_clksel_by_parent(struct clk clk,

		if (!clks->parent) {
		/* This indicates a data problem */
		WARN(1, "clock: Could not find parent clock %s in clksel array "
		"of clock %s\n", src_clk->name, clk->name);
		WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
		__clk_get_name(clk), __clk_get_name(src_clk));
		return NULL;
		}

		@@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk src_clk, struct clk clk,

		if (max_div == 0) {
		/* This indicates an error in the clksel data */
		WARN(1, "clock: Could not find divisor for clock %s parent %s"
		"\n", clk->name, src_clk->parent->name);
		WARN(1, "clock: %s: could not find divisor for parent %s\n",
		__clk_get_name(clk),
		__clk_get_name(__clk_get_parent(src_clk)));
		return 0;
		}

		@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
		{
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		struct clk *parent;

		clks = _get_clksel_by_parent(clk, clk->parent);
		parent = __clk_get_parent(clk);
		clks = _get_clksel_by_parent(clk, parent);
		if (!clks)
		return 0;

		@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)

		if (!clkr->div) {
		/* This indicates a data error */
		WARN(1, "clock: Could not find fieldval %d for clock %s parent "
		"%s\n", field_val, clk->name, clk->parent->name);
		WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
		__clk_get_name(clk), field_val, __clk_get_name(parent));
		return 0;
		}

		@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
		{
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		struct clk *parent;

		/* should never happen */
		WARN_ON(div == 0);

		clks = _get_clksel_by_parent(clk, clk->parent);
		parent = __clk_get_parent(clk);
		clks = _get_clksel_by_parent(clk, parent);
		if (!clks)
		return ~0;

		@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
		}

		if (!clkr->div) {
		pr_err("clock: Could not find divisor %d for clock %s parent "
		"%s\n", div, clk->name, clk->parent->name);
		pr_err("clock: %s: could not find divisor %d for parent %s\n",
		__clk_get_name(clk), div, __clk_get_name(parent));
		return ~0;
		}

		@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		u32 last_div = 0;
		struct clk *parent;
		unsigned long parent_rate;
		const char *clk_name;

		parent = __clk_get_parent(clk);
		parent_rate = __clk_get_rate(parent);
		clk_name = __clk_get_name(clk);

		if (!clk->clksel \|\| !clk->clksel_mask)
		return ~0;

		pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
		clk->name, target_rate);
		clk_name, target_rate);

		*new_div = 1;

		clks = _get_clksel_by_parent(clk, clk->parent);
		clks = _get_clksel_by_parent(clk, parent);
		if (!clks)
		return ~0;

		@@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,

		/* Sanity check */
		if (clkr->div <= last_div)
		pr_err("clock: clksel_rate table not sorted "
		"for clock %s", clk->name);
		pr_err("clock: %s: clksel_rate table not sorted\n",
		clk_name);

		last_div = clkr->div;

		test_rate = clk->parent->rate / clkr->div;
		test_rate = parent_rate / clkr->div;

		if (test_rate <= target_rate)
		break; /* found it */
		}

		if (!clkr->div) {
		pr_err("clock: Could not find divisor for target "
		"rate %ld for clock %s parent %s\n", target_rate,
		clk->name, clk->parent->name);
		pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
		clk_name, target_rate, __clk_get_name(parent));
		return ~0;
		}

		*new_div = clkr->div;

		pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
		(clk->parent->rate / clkr->div));
		(parent_rate / clkr->div));

		return clk->parent->rate / clkr->div;
		return parent_rate / clkr->div;
		}

		/*
		@@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
		const struct clksel *clks;
		const struct clksel_rate *clkr;
		u32 r, found = 0;
		struct clk *parent;
		const char *clk_name;

		if (!clk->clksel \|\| !clk->clksel_mask)
		return;

		parent = __clk_get_parent(clk);
		clk_name = __clk_get_name(clk);

		r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
		r >>= __ffs(clk->clksel_mask);

		@@ -358,12 +374,14 @@ void omap2_init_clksel_parent(struct clk *clk)
		continue;

		if (clkr->val == r) {
		if (clk->parent != clks->parent) {
		if (parent != clks->parent) {
		pr_debug("clock: inited %s parent "
		"to %s (was %s)\n",
		clk->name, clks->parent->name,
		((clk->parent) ?
		clk->parent->name : "NULL"));
		clk_name,
		__clk_get_name(clks->parent),
		((parent) ?
		__clk_get_name(parent) :
		"NULL"));
		clk_reparent(clk, clks->parent);
		};
		found = 1;
		@@ -373,7 +391,7 @@ void omap2_init_clksel_parent(struct clk *clk)

		/* This indicates a data error */
		WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
		clk->name, r);
		clk_name, r);

		return;
		}
		@@ -391,15 +409,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
		{
		unsigned long rate;
		u32 div = 0;
		struct clk *parent;

		div = _read_divisor(clk);
		if (div == 0)
		return clk->rate;
		return __clk_get_rate(clk);

		rate = clk->parent->rate / div;
		parent = __clk_get_parent(clk);
		rate = __clk_get_rate(parent) / div;

		pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
		rate, div);
		pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
		__clk_get_name(clk), rate, div);

		return rate;
		}
		@@ -454,9 +474,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)

		_write_clksel_reg(clk, field_val);

		clk->rate = clk->parent->rate / new_div;
		clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;

		pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
		pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
		__clk_get_rate(clk));

		return 0;
		}
		@@ -498,13 +519,15 @@ int omap2_clksel_set_parent(struct clk clk, struct clk new_parent)
		clk_reparent(clk, new_parent);

		/* CLKSEL clocks follow their parents' rates, divided by a divisor */
		clk->rate = new_parent->rate;
		clk->rate = __clk_get_rate(new_parent);

		if (parent_div > 0)
		clk->rate /= parent_div;
		__clk_get_rate(clk) /= parent_div;

		pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
		clk->name, clk->parent->name, clk->rate);
		__clk_get_name(clk),
		__clk_get_name(__clk_get_parent(clk)),
		__clk_get_rate(clk));

		return 0;
		}

arch/arm/mach-omap2/clkt_dpll.c

+15 −11

Original line number	Diff line number	Diff line
		@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
		dd = clk->dpll_data;

		/* DPLL divider must result in a valid jitter correction val */
		fint = clk->parent->rate / n;
		fint = __clk_get_rate(__clk_get_parent(clk)) / n;

		if (cpu_is_omap24xx()) {
		/* Should not be called for OMAP2, so warn if it is called */
		@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
		if (cpu_is_omap24xx()) {
		if (v == OMAP2XXX_EN_DPLL_LPBYPASS \|\|
		v == OMAP2XXX_EN_DPLL_FRBYPASS)
		return dd->clk_bypass->rate;
		return __clk_get_rate(dd->clk_bypass);
		} else if (cpu_is_omap34xx()) {
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS \|\|
		v == OMAP3XXX_EN_DPLL_FRBYPASS)
		return dd->clk_bypass->rate;
		return __clk_get_rate(dd->clk_bypass);
		} else if (soc_is_am33xx() \|\| cpu_is_omap44xx()) {
		if (v == OMAP4XXX_EN_DPLL_LPBYPASS \|\|
		v == OMAP4XXX_EN_DPLL_FRBYPASS \|\|
		v == OMAP4XXX_EN_DPLL_MNBYPASS)
		return dd->clk_bypass->rate;
		return __clk_get_rate(dd->clk_bypass);
		}

		v = __raw_readl(dd->mult_div1_reg);
		@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
		dpll_div = v & dd->div1_mask;
		dpll_div >>= __ffs(dd->div1_mask);

		dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
		dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
		do_div(dpll_clk, dpll_div + 1);

		return dpll_clk;
		@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
		unsigned long scaled_rt_rp;
		unsigned long new_rate = 0;
		struct dpll_data *dd;
		unsigned long ref_rate;
		const char *clk_name;

		if (!clk \|\| !clk->dpll_data)
		return ~0;

		dd = clk->dpll_data;

		ref_rate = __clk_get_rate(dd->clk_ref);
		clk_name = __clk_get_name(clk);
		pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
		clk->name, target_rate);
		clk_name, target_rate);

		scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
		scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
		scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;

		dd->last_rounded_rate = 0;
		@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
		break;

		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
		dd->clk_ref->rate);
		ref_rate);

		/* m can't be set low enough for this n - try with a larger n */
		if (r == DPLL_MULT_UNDERFLOW)
		continue;

		pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
		clk->name, m, n, new_rate);
		clk_name, m, n, new_rate);

		if (target_rate == new_rate) {
		dd->last_rounded_m = m;
		@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
		}

		if (target_rate != new_rate) {
		pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
		target_rate);
		pr_debug("clock: %s: cannot round to rate %ld\n",
		clk_name, target_rate);
		return ~0;
		}

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