RISC-V: recognize S/U mode bits in print_isa (5d8f81ba) · Commits · 戴 / test

Removes the warning about an unsupported ISA when reading /proc/cpuinfo on QEMU. The "S" extension is not being returned as it is not accessible from userspace. Signed-off-by:

Patrick Stählin <me@packi.ch> Signed-off-by:

Palmer Dabbelt <palmer@sifive.com>

arch/riscv/kernel/cpu.c

+6 −3

Original line number	Diff line number	Diff line
		@@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node)

		static void print_isa(struct seq_file f, const char orig_isa)
		{
		static const char *ext = "mafdc";
		static const char *ext = "mafdcsu";
		const char *isa = orig_isa;
		const char *e;

		@@ -88,11 +88,14 @@ static void print_isa(struct seq_file f, const char orig_isa)
		/*
		* Check the rest of the ISA string for valid extensions, printing those
		* we find. RISC-V ISA strings define an order, so we only print the
		* extension bits when they're in order.
		* extension bits when they're in order. Hide the supervisor (S)
		* extension from userspace as it's not accessible from there.
		*/
		for (e = ext; *e != '\0'; ++e) {
		if (isa[0] == e[0]) {
		if (isa[0] != 's')
		seq_write(f, isa, 1);

		isa++;
		}
		}

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