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Receiving an interrupt whose Interrupt Status Register value has only the SRX bit set is supposed to mean that all of the data from the tag has been received. That turns out to not be true so we need to reread the FIFO Status Register to tell if there are any new bytes in the FIFO. If there are, continue receiving them; if there aren't, assume that the receive is complete and pass the data up. Signed-off-by:Mark A. Greer <mgreer@animalcreek.com> Signed-off-by:
Samuel Ortiz <sameo@linux.intel.com>
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