Merge tag 'samsung-dt-dmc-5.5' of...

  "lpddr2-timings" provides AC timing parameters of the device for

  a given speed-bin. The user may provide the timings for as many

  speed-bins as is required. Please see Documentation/devicetree/

  bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"

  bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"

Example:

* AC timing parameters of LPDDR3 memories for a given speed-bin.

The structures are based on LPDDR2 and extended where needed.

Required properties:

- compatible : Should be "jedec,lpddr3-timings"

- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>

- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>

Optional properties:

The following properties represent AC timing parameters from the memory

data-sheet of the device for a given speed-bin. All these properties are

of type <u32> and the default unit is ps (pico seconds).

- tRFC

- tRRD

- tRPab

- tRPpb

- tRCD

- tRC

- tRAS

- tWTR

- tWR

- tRTP

- tW2W-C2C

- tR2R-C2C

- tFAW

- tXSR

- tXP

- tCKE

- tCKESR

- tMRD

Example:

timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {

	compatible	= "jedec,lpddr3-timings";

	reg		= <800000000>; /* workaround: it shows max-freq */

	min-freq	= <100000000>;

	tRFC		= <65000>;

	tRRD		= <6000>;

	tRPab		= <12000>;

	tRPpb		= <12000>;

	tRCD		= <10000>;

	tRC		= <33750>;

	tRAS		= <23000>;

	tWTR		= <3750>;

	tWR		= <7500>;

	tRTP		= <3750>;

	tW2W-C2C	= <0>;

	tR2R-C2C	= <0>;

	tFAW		= <25000>;

	tXSR		= <70000>;

	tXP		= <3750>;

	tCKE		= <3750>;

	tCKESR		= <3750>;

	tMRD		= <7000>;

};

* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C

Required properties:

- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".

  Example "<vendor>,<type>" values:

    "samsung,K3QF2F20DB"

- density  : <u32> representing density in Mb (Mega bits)

- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64

- #address-cells: Must be set to 1

- #size-cells: Must be set to 0

Optional properties:

The following optional properties represent the minimum value of some AC

timing parameters of the DDR device in terms of number of clock cycles.

These values shall be obtained from the device data-sheet.

- tRFC-min-tck

- tRRD-min-tck

- tRPab-min-tck

- tRPpb-min-tck

- tRCD-min-tck

- tRC-min-tck

- tRAS-min-tck

- tWTR-min-tck

- tWR-min-tck

- tRTP-min-tck

- tW2W-C2C-min-tck

- tR2R-C2C-min-tck

- tWL-min-tck

- tDQSCK-min-tck

- tRL-min-tck

- tFAW-min-tck

- tXSR-min-tck

- tXP-min-tck

- tCKE-min-tck

- tCKESR-min-tck

- tMRD-min-tck

Child nodes:

- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".

  "lpddr3-timings" provides AC timing parameters of the device for

  a given speed-bin. Please see Documentation/devicetree/

  bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings"

Example:

samsung_K3QF2F20DB: lpddr3 {

	compatible	= "samsung,K3QF2F20DB", "jedec,lpddr3";

	density		= <16384>;

	io-width	= <32>;

	#address-cells	= <1>;

	#size-cells	= <0>;

	tRFC-min-tck		= <17>;

	tRRD-min-tck		= <2>;

	tRPab-min-tck		= <2>;

	tRPpb-min-tck		= <2>;

	tRCD-min-tck		= <3>;

	tRC-min-tck		= <6>;

	tRAS-min-tck		= <5>;

	tWTR-min-tck		= <2>;

	tWR-min-tck		= <7>;

	tRTP-min-tck		= <2>;

	tW2W-C2C-min-tck	= <0>;

	tR2R-C2C-min-tck	= <0>;

	tWL-min-tck		= <8>;

	tDQSCK-min-tck		= <5>;

	tRL-min-tck		= <14>;

	tFAW-min-tck		= <5>;

	tXSR-min-tck		= <12>;

	tXP-min-tck		= <2>;

	tCKE-min-tck		= <2>;

	tCKESR-min-tck		= <2>;

	tMRD-min-tck		= <5>;

	timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {

		compatible	= "jedec,lpddr3-timings";

		/* workaround: 'reg' shows max-freq */

		reg		= <800000000>;

		min-freq	= <100000000>;

		tRFC		= <65000>;

		tRRD		= <6000>;

		tRPab		= <12000>;

		tRPpb		= <12000>;

		tRCD		= <10000>;

		tRC		= <33750>;

		tRAS		= <23000>;

		tWTR		= <3750>;

		tWR		= <7500>;

		tRTP		= <3750>;

		tW2W-C2C	= <0>;

		tR2R-C2C	= <0>;

		tFAW		= <25000>;

		tXSR		= <70000>;

		tXP		= <3750>;

		tCKE		= <3750>;

		tCKESR		= <3750>;

		tMRD		= <7000>;

	};

}

* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device

The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM

memory chips are connected. The driver is to monitor the controller in runtime

and switch frequency and voltage. To monitor the usage of the controller in

runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which

is able to measure the current load of the memory.

When 'userspace' governor is used for the driver, an application is able to

switch the DMC and memory frequency.

Required properties for DMC device for Exynos5422:

- compatible: Should be "samsung,exynos5422-dmc".

- clocks : list of clock specifiers, must contain an entry for each

  required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,

  CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,

  CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,

- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",

  "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",

  "mout_mclk_cdrex"  entries

- devfreq-events : phandles for PPMU devices connected to this DMC.

- vdd-supply : phandle for voltage regulator which is connected.

- reg : registers of two CDREX controllers.

- operating-points-v2 : phandle for OPPs described in v2 definition.

- device-handle : phandle of the connected DRAM memory device. For more

	information please refer to documentation file:

	Documentation/devicetree/bindings/ddr/lpddr3.txt

- devfreq-events : phandles of the PPMU events used by the controller.

- samsung,syscon-clk : phandle of the clock register set used by the controller,

	these registers are used for enabling a 'pause' feature and are not

	exposed by clock framework but they must be used in a safe way.

	The register offsets are in the driver code and specyfic for this SoC

	type.

Optional properties for DMC device for Exynos5422:

- interrupt-parent : The parent interrupt controller.

- interrupts : Contains the IRQ line numbers for the DMC internal performance

  event counters in DREX0 and DREX1 channels. Align with specification of the

  interrupt line(s) in the interrupt-parent controller.

- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the

  same as in the 'interrupts' list above.

Example:

	ppmu_dmc0_0: ppmu@10d00000 {

		compatible = "samsung,exynos-ppmu";

		reg = <0x10d00000 0x2000>;

		clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;

		clock-names = "ppmu";

		events {

			ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {

				event-name = "ppmu-event3-dmc0_0";

			};

		};

	};

	dmc: memory-controller@10c20000 {

		compatible = "samsung,exynos5422-dmc";

		reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;

		clocks = <&clock CLK_FOUT_SPLL>,

			 <&clock CLK_MOUT_SCLK_SPLL>,

			 <&clock CLK_FF_DOUT_SPLL2>,

			 <&clock CLK_FOUT_BPLL>,

			 <&clock CLK_MOUT_BPLL>,

			 <&clock CLK_SCLK_BPLL>,

			 <&clock CLK_MOUT_MX_MSPLL_CCORE>,

			 <&clock CLK_MOUT_MCLK_CDREX>;

		clock-names = "fout_spll",

			      "mout_sclk_spll",

			      "ff_dout_spll2",

			      "fout_bpll",

			      "mout_bpll",

			      "sclk_bpll",

			      "mout_mx_mspll_ccore",

			      "mout_mclk_cdrex";

		operating-points-v2 = <&dmc_opp_table>;

		devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,

				 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;

		device-handle = <&samsung_K3QF2F20DB>;

		vdd-supply = <&buck1_reg>;

		samsung,syscon-clk = <&clock>;

		interrupt-parent = <&combiner>;

		interrupts = <16 0>, <16 1>;

		interrupt-names = "drex_0", "drex_1";

	};