scsi: ufs-mediatek: configure and enable clk-gating (5d74e18e) · Commits · 戴 / test

Enable clk-gating with customized delayed timer value in MediaTek Chipsets. Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Avri Altman <avri.altman@wdc.com> Cc: Bart Van Assche <bvanassche@acm.org> Cc: Bean Huo <beanhuo@micron.com> Cc: Can Guo <cang@codeaurora.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/1577683950-1702-7-git-send-email-stanley.chu@mediatek.com Reviewed-by:

Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by:

Stanley Chu <stanley.chu@mediatek.com> Signed-off-by:

Martin K. Petersen <martin.petersen@oracle.com>

drivers/scsi/ufs/ufs-mediatek.c

+22 −0

Original line number	Diff line number	Diff line
		@@ -210,6 +210,9 @@ static int ufs_mtk_init(struct ufs_hba *hba)
		/* Enable runtime autosuspend */
		hba->caps \|= UFSHCD_CAP_RPM_AUTOSUSPEND;

		/* Enable clock-gating */
		hba->caps \|= UFSHCD_CAP_CLK_GATING;

		/*
		* ufshcd_vops_init() is invoked after
		* ufshcd_setup_clock(true) in ufshcd_hba_init() thus
		@@ -298,6 +301,23 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba)
		return ret;
		}

		static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
		{
		unsigned long flags;
		u32 ah_ms;

		if (ufshcd_is_clkgating_allowed(hba)) {
		if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
		ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
		hba->ahit);
		else
		ah_ms = 10;
		spin_lock_irqsave(hba->host->host_lock, flags);
		hba->clk_gating.delay_ms = ah_ms + 5;
		spin_unlock_irqrestore(hba->host->host_lock, flags);
		}
		}

		static int ufs_mtk_post_link(struct ufs_hba *hba)
		{
		/* disable device LCC */
		@@ -313,6 +333,8 @@ static int ufs_mtk_post_link(struct ufs_hba *hba)
		FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
		}

		ufs_mtk_setup_clk_gating(hba);

		return 0;
		}

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