Commit 5d5b71e8 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add the GC 10.3 VRS registers 



Add the VRS registers.

Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1d0e16ac

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h

+2 −0
Original line number Diff line number Diff line
@@ -2727,6 +2727,7 @@ 
#define mmDB_STENCIL_WRITE_BASE_DEFAULT                                          0x00000000

#define mmDB_RESERVED_REG_1_DEFAULT                                              0x00000000

#define mmDB_RESERVED_REG_3_DEFAULT                                              0x00000000

#define mmDB_VRS_OVERRIDE_CNTL_DEFAULT                                           0x00000000

#define mmDB_Z_READ_BASE_HI_DEFAULT                                              0x00000000

#define mmDB_STENCIL_READ_BASE_HI_DEFAULT                                        0x00000000

#define mmDB_Z_WRITE_BASE_HI_DEFAULT                                             0x00000000
@@ -3062,6 +3063,7 @@ 
#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT                                  0x00000000

#define mmPA_STEREO_CNTL_DEFAULT                                                 0x00000000

#define mmPA_STATE_STEREO_X_DEFAULT                                              0x00000000

#define mmPA_CL_VRS_CNTL_DEFAULT                                                 0x00000000

#define mmPA_SU_POINT_SIZE_DEFAULT                                               0x00000000

#define mmPA_SU_POINT_MINMAX_DEFAULT                                             0x00000000

#define mmPA_SU_LINE_CNTL_DEFAULT                                                0x00000000

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

+4 −0
Original line number Diff line number Diff line
@@ -5379,6 +5379,8 @@ 
#define mmDB_RESERVED_REG_1_BASE_IDX                                                                   1

#define mmDB_RESERVED_REG_3                                                                            0x0017

#define mmDB_RESERVED_REG_3_BASE_IDX                                                                   1

#define mmDB_VRS_OVERRIDE_CNTL                                                                         0x0019

#define mmDB_VRS_OVERRIDE_CNTL_BASE_IDX                                                                1

#define mmDB_Z_READ_BASE_HI                                                                            0x001a

#define mmDB_Z_READ_BASE_HI_BASE_IDX                                                                   1

#define mmDB_STENCIL_READ_BASE_HI                                                                      0x001b
@@ -6049,6 +6051,8 @@ 
#define mmPA_STEREO_CNTL_BASE_IDX                                                                      1

#define mmPA_STATE_STEREO_X                                                                            0x0211

#define mmPA_STATE_STEREO_X_BASE_IDX                                                                   1

#define mmPA_CL_VRS_CNTL                                                                               0x0212

#define mmPA_CL_VRS_CNTL_BASE_IDX                                                                      1

#define mmPA_SU_POINT_SIZE                                                                             0x0280

#define mmPA_SU_POINT_SIZE_BASE_IDX                                                                    1

#define mmPA_SU_POINT_MINMAX                                                                           0x0281

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

+50 −0

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